PDF SEP02G72E2BF2SA-30R Data sheet ( Hoja de datos )

Número de pieza	SEP02G72E2BF2SA-30R
Descripción	SDRAM registered DIMM
Fabricantes	Swissbit
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No Preview Available ! Data Sheet Rev.1.0 23.11.2010 2GB DDR2 – SDRAM registered DIMM 240 Pin RDIMM SEP02G72E2BF2SA-30R 2GB PC2-5300 in FBGA Technology RoHS compliant Options:  Data Rate / Latency DDR2 533 MTs / CL4 DDR2 667 MT/s / CL5 Marking -37 -30  Module Density 2048MB with 18 dies and 2 ranks  Standard Grade (TA) (TC) 0°C to 70°C 0°C to 85°C Environmental Requirements:  Operating temperature (TAMBIENT) Standard Grade  Operating Humidity 0°C to 70°C 10% to 90% relative humidity, noncondensing  Operating Pressure 105 to 69 kPa (up to 10000 ft.)  Storage Temperature -55°C to 100°C  Storage Humidity 5% to 95% relative humidity, noncondensing  Storage Pressure 1682 PSI (up to 5000 ft.) at 50°C Features:  240-pin 72-bit DDR2 registered Dual-In-Line Double Data Rate Synchronous DRAM Module for server applications  Module organization: dual rank 256M x 72  VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V  1.8V I/O ( SSTL_18 compatible)  Serial Presence Detect with EEPROM  Supports ECC error detection and correction  JEDEC compatible DDR2 PLL/Register component with parity bit support for address and control bus  Gold-contact pad  This module family is fully pin and functional compatible to JEDEC. (see www.jedec.org)  The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)]  DDR2 SDRAM component Samsung K4T1G084QF  128Mx8 DDR2 SDRAM in FBGA-60 package  Four bit prefetch architecture  Programmable CAS latency (CL)  Posted CAS additive latency (AL)  WRITE latency = READ latency – 1 tCK  Programmable burst length: 4 or 8  Adjustable data-output drive strength  On-die termination (ODT)  DLL to align DQ and DQS transitions with CK Figure: mechanical dimensions1 Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 1if no tolerances specified ± 0.15mm www.swissbit.com eMail: [email protected] Page 1 of 14 1 page Data Sheet Rev.1.0 23.11.2010 FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR2 ECC Registered DIMM, 2 RANKS AND 18 COMPONENTS Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: [email protected] Page 5 of 14 5 Page Data Sheet Rev.1.0 23.11.2010 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V) AC CHARACTERISTICS PARAMETER ODT power-down exit latency ODT enable from MRS command Exit active power-down to READ command, MR [bit 12 = 0] Exit active power-down to READ command, MR [bit 12 = 1] Exit precharge power-down to any non-READ command CKE minimum high/low time SYMBOL tAXPD TMOD 5300-555 MIN MAX 8 0 12 tXARD 2 tXARDS 7 – AL tXP tCKE 2 3 4200-444 MIN MAX 8 0 12 Unit tCK ns 2 tCK 6 – AL tCK 2 tCK 3 tCK Register Specifications Parameter DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage Output high voltage Output low voltage Input current Static standby Static operating Dynamic operating (clock tree) Dynamic operating (per each input) Input capacitance (per device, per pin) Input capacitance (per device, per pin) Symbol VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH VOL II IDD Pins Address, control, command Address, control, command Address, control, command Address, control, command Parity output Parity output All pins All pins IDD All pins IDDD n/a IDDD n/a CI Data CI RESET# Conditions SSTL_18 SSTL_18 SSTL_18 SSTL_18 LVCMOS LVCMOS VI = VDDQ or VSSQ RESET# = VSSQ (IO = 0) RESET# = VSSQ; VI = VIH(AC) or VIL(DC) IO = 0 RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle; One data input switching at tCK/2, 50% duty cycle VI = VREF ±250mV; VDDQ = 1.8V VI = VDDQ or VSSQ Min Max Units VREF(DC) + 125 VDDQ + 250 mV 0 VREF(DC) - 125 mV VREF(DC) + 250 VDD mV 0 VREF(DC) - 250 mV 1.2 - V - 0.5 V -5 +5 µA - 100 µA - 40 mA - Varies by manufacturer µA - Varies by manufacturer µA 2.5 3.5 pF - Varies by manufacturer pF Notes: 1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR2 SDRAM registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC standard JESD82. Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: [email protected] Page 11 of 14 11 Page

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