PDF RML1371MH48D7F-667A Data sheet ( Hoja de datos )

Número de pieza	RML1371MH48D7F-667A
Descripción	DDR2 SDRAM / 240Pin Unbuffered DIMM
Fabricantes	Ramaxel
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No Preview Available ! RML1371MH48D7F-667A DATA SHEET DDR2 SDRAM 240Pin Unbuffered DIMM Based on Micron 1Gb H-die 60-ball FBGA With Lead-Free (RoHS compliant) Ramaxel Technology reserves the right to change products or specifications without notice. © 2013 Ramaxel Technology Co., Ltd. All rights reserved. Ver1.0 / Dec. 2013 1/11 1 page Pin Assignments RML1371MH48D7F-667A Pin Front Pin # Side # Back Side Pin Front Pin # Side # Back Side Pin Front Pin # Side # Back Side Pin Front Pin # Side # Back Side 1 VREF 121 VSS 31 DQ19 151 VSS 61 A4 181 VDDQ 91 VSS 211 DM5/DQS14 2 VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS5 212 NC, DQS14 3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS 4 DQ1 124 VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46 5 VSS 125 DM0/DQS9 35 VSS 155 DM3/DQS12 KEY 95 DQ42 215 DQ47 6 DQS0 126 NC, DQS9 36 DQS3 156 NC, DQS12 65 VSS 185 CK0 96 DQ43 216 VSS 7 DQS0 127 VSS 37 DQS3 157 VSS 66 VSS 186 CK0 97 VSS 217 DQ52 8 VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48 218 DQ53 9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC, Par_In 188 A0 99 DQ49 219 VSS 10 DQ3 130 VSS 40 DQ27 160 VSS 69 VDD 189 VDD 100 VSS 220 RFU, S2 11 VSS 131 DQ12 41 VSS 161 CB4 70 A10/ AP 190 BA1 101 SA2 221 RFU, S3 12 DQ8 132 DQ13 42 CB0 162 CB5 71 BA0 191 VDDQ 102 NC(TEST) 222 VSS 13 DQ9 133 VSS 43 CB1 163 VSS 72 VDDQ 192 RAS 103 VSS 223 DM6/DQS15 14 VSS 134 DM1/DQS10 44 VSS 164 DM8/DQS17 73 WE 193 S0 104 DQS6 224 NC, DQS15 15 DQS1 135 NC, DQS10 45 DQS8 165 NC, DQS17 74 CAS 194 VDDQ 105 DQS6 225 VSS 16 DQS1 136 VSS 46 DQS8 166 VSS 75 VDDQ 195 ODT0 106 VSS 226 DQ54 17 VSS 137 RFU 47 VSS 167 CB6 76 NC, S1 196 A13, NC 107 DQ50 227 DQ55 18 RESET 138 RFU 48 CB2 168 CB7 77 NC, ODT1 197 VDD 108 DQ51 228 VSS 19 NC 139 VSS 49 CB3 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60 20 VSS 140 DQ14 50 VSS 170 VDDQ 79 VSS 199 DQ36 110 DQ56 230 DQ61 21 DQ10 141 DQ15 51 VDDQ 171 NC, CKE1 80 DQ32 200 DQ37 111 DQ57 231 VSS 22 DQ11 142 VSS 52 CKE0 172 VDD 81 DQ33 201 VSS 112 VSS 232 DM7/DQS16 23 VSS 143 DQ20 53 VDD 173 A15, NC 82 VSS 202 DM4/DQS13 113 DQS7 233 NC, DQS16 24 DQ16 144 DQ21 54 BA2, NC 174 A14, NC 83 DQS4 203 NC, DQS13 114 DQS7 234 VSS 25 DQ17 145 VSS 55 NC, Err_Out 175 VDDQ 84 DQS4 204 VSS 115 VSS 235 DQ62 26 VSS 146 DM2/DQS11 56 VDDQ 176 A12 85 VSS 205 DQ38 116 DQ58 236 DQ63 27 DQS2 147 NC, DQS11 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 VSS 28 DQS2 148 VSS 58 A7 178 VDD 87 DQ35 207 VSS 118 VSS 238 VDDSPD 29 VSS 149 DQ22 59 VDD 179 A8 88 VSS 208 DQ44 119 SDA 239 SA0 30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1 90 DQ41 210 VSS NC = No Connect; NU = Not Useable, RFU = Reserved Future Use. 1. CK1,CK1,CK2, CK2 (pins 137,138,220,221) are for Unbuffered DIMM clock. Pins 137, 138 are RFU on registered DIMMs; pins 220, 221 are used for 4 rank RDIMMs. 2. RESET (pin 18) is connected to both OE of the PLL and Reset of the register. 3. The TEST pin (pin 102) is reserved for bus analysis probes and is not connected on normal modules (DIMMs). 4. NC/Err_Out (pin 55) and NC/Par_In (pin 68) are optional function to check address and command parity. Ver1.0 / Dec. 2013 5/11 5 Page RML1371MH48D7F-667A CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stresson these components to prevent damaging them.In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other.Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. NOTES FOR CMOS DEVICES 1) PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2) HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3) STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Ver1.0 / Dec. 2013 11/11 11 Page

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