PDF K4H561638N Data sheet ( Hoja de datos )

Número de pieza	K4H561638N
Descripción	256Mb N-die DDR SDRAM
Fabricantes	Samsung
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No Preview Available ! Rev. 1.01, May. 2010 K4H560438N K4H560838N K4H561638N 256Mb N-die DDR SDRAM 66TSOP-(II) with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved. -1- 1 page K4H560438N K4H560838N K4H561638N datasheet Rev. 1.01 DDR SDRAM 4. Pin / Ball Description 16Mb x 16 32Mb x 8 64Mb x 4 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 66 2 65 3 64 4 63 5 62 6 61 7 60 8 59 9 58 10 66Pin TSOPII 57 11 (400mil x 875mil) 56 12 (0.65mm Pin Pitch) 55 13 54 14 53 15 Bank Address BA0~BA1 52 16 51 17 50 18 19 Auto Precharge A10 49 48 20 47 21 46 22 45 23 44 24 43 25 42 26 41 27 40 28 39 29 38 30 37 31 36 32 35 33 34 256Mb TSOP-II Package Pinout VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS Organization 64Mx4 32Mx8 16Mx16 Row Address A0~A12 A0~A12 A0~A12 Column Address A0-A9, A11 A0-A9 A0-A8 DM is internally loaded to match DQ and DQS identically. Figure 1. Row & Column address configuration -5- 5 Page K4H560438N K4H560838N K4H561638N datasheet Rev. 1.01 DDR SDRAM 12. DDR SDRAM Spec Items & Test Conditions Conditions Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition Precharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; VIN = VREF for DQ,DQS and DM. Precharge Floating standby current; CS > =VIH(min);All banks idle; CKE > = VIH(min); tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ,DQS and DM Precharge Quiet standby current; CS > = VIH(min); All banks idle; CKE > = VIH(min); tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs stable at >= VIH(min) or =<VIL(max); VIN = VREF for DQ ,DQS and DM Active power - down standby current ; one bank active; power-down mode; CKE=< VIL (max); tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Vin = Vref for DQ,DQS and DM Active standby current; CS >= VIH(min); CKE>=VIH(min); one bank active; tRC=tRASmax; tCK=10ns for DDR200,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at 7.5ns for DDR266, CL=2.5 at tCK=7.5ns for DDR266, tCK=6ns for DDR333, CL=3 at tCK=5ns for DDR400; 50% of data changing on every transfer; lout = 0 m A Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL=2 at tCK=10ns for DDR200, CL=2 at tCK=7.5ns for DDR266, CL=2.5 at tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst Auto refresh current; tRC = tRFC(min) which is 8tCK for DDR200 at tCK=10ns; 10tCK for DDR266 at tCK=7.5ns; 12tCK for DDR333 at tCK=6ns, 14tCK for DDR400 at tCK=5ns; distributed refresh Self refresh current; CKE =< 0.2V; External clock on; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400. Operating current - Four bank operation ; Four bank interleaving with BL=4 -Refer to the following page for detailed test condition Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A 13. Input/Output Capacitance ( TA= 25°C, f=100MHz) Parameter Symbol Min Max DeltaCap(max) Unit NOTE Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) CIN1 2 3 0.5 pF 4 Input capacitance( CK, CK ) CIN2 2 3 0.25 pF 4 Data & DQS input/output capacitance Input capacitance(DM for x4/8, UDM/LDM for x16) COUT CIN3 4 4 5 5 pF 1,2,3,4 0.5 pF 1,2,3,4 NOTE : 1.These values are guaranteed by design and are tested on a sample basis only. 2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system. 3. Unused pins are tied to ground. 4. This parameteer is sampled. VDDQ = +2.5V +0.2V, VDD = +2.5V+0.2V. For all devices, f=100MHz, tA=25°C, VOUT(DC) = VDDQ/2, VOUT(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). - 11 - 11 Page

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