PDF K4M51163PI-BG75 Data sheet ( Hoja de datos )

Número de pieza	K4M51163PI-BG75
Descripción	512Mb I-die Mobile SDR SDRAM
Fabricantes	Samsung semiconductor
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No Preview Available ! Rev. 1.0, Dec. 2009 K4M51163PI 512Mb I-die Mobile SDR SDRAM 32Mb x16, 54FBGA with Lead-Free & Halogen-Free (VDD / VDDQ = 1.8V / 1.8V) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2009 Samsung Electronics Co., Ltd. All rights reserved. -1- 1 page K4M51163PI-8G60 K4M51163PI-8G75 datasheet 5.0 FUNCTIONAL BLOCK DIAGRAM Rev. 1.0 Mobile DDR SDRAM Bank Select CLK ADD Data Input Register 8M x 16 8M x 16 8M x 16 8M x 16 Column Decoder LCKE LRAS LCBR LWE LCAS Latency & Burst Length Programming Register LWCBR Timing Register CLK CKE CS RAS CAS WE DQM LWE LDQM DQi LDQM -5- 5 Page K4M51163PI-8G60 K4M51163PI-8G75 datasheet Rev. 1.0 Mobile DDR SDRAM 13.0 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol CLK cycle time CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ -60 Min Max 6.0 1000 - 5.4 - 2.5 - 2.5 2.5 2.0 1 1 5.4 - -75 Min Max 7.5 1000 12 6 9 2.5 2.5 2.5 2.5 2.0 1 1 6 9 NOTE : 1) Parameters depend on programmed CAS latency. 2) tCC(max) value is measured at 100ns. 3) The only time that the clock Frequency is allowed to be changed is during clock stop, power-down, self-refresh modes. 4) If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 5) Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Unit Note ns 1,2,3 ns 1,4 ns 4 ns 5 ns 5 ns 5 ns 5 ns 4 ns - 11 - 11 Page

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Número de pieza	Descripción	Fabricantes
K4M51163PI-BG75	512Mb I-die Mobile SDR SDRAM	Samsung semiconductor

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