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PDF TDA19998HL Data sheet ( Hoja de datos )
| Número de pieza | TDA19998HL | |
| Descripción | Smart HDMI 1.4a (4:1) switch | |
| Fabricantes | NXP Semiconductors | |
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TDA19998HL
Smart HDMI 1.4a (4 : 1) switch with auto-adaptive equalizer
Rev. 3 — 4 August 2010
Product data sheet
1. General description
The High-Definition Multimedia Interface (HDMI) switch enables connection of multiple
DVI/HDMI inputs to a receiver with at least one input. The TDA19998HL is a switch with
four HDMI 1.4a compliant DVI/HDMI inputs and one DVI/HDMI output. Each HDMI input
has its own dedicated embedded EDID memory. A fifth DDC-bus input is available for
VGA or second HDMI input of SoC. The built-in auto-adaptive equalizer improves signal
quality, allowing the use of cable lengths up to 30 m.
The TDA19998HL supports Deep Color mode in 10-bit and 12-bit per channel up to
1920 × 1080p at 50/60 Hz. The TDA19998HL supports DVI/HDMI streams with or without
High-bandwidth Digital Content Protection (HDCP 1.4) and all Data Island packets.
The TDA19998HL settings are controllable via the I2C-bus.
The TDA19998HL, pin compatible with TDA19997, is embedding the "F3 technology" from
NXP, allowing no delay in switching from one HDMI port to any other HDMI port while
keeping HDMI output stream encrypted.
2. Features and benefits
Complies with the HDMI 1.4a, DVI 1.0, EIA/CEA-861D and HDCP 1.4 standards
Four independent DVI/HDMI inputs, up to 2.25 gigasamples per second
Pin compatible with TDA9996/TDA9995/TDA19997/TDA19995
"F3 technology" for fast switching HDMI port
Robust auto-adaptive equalizer
up to 20 m AWG26 at 2.25 Gbit/s
up to 30 m AWG24 at 1.5 Gbit/s
Integrated 50 Ω single-ended termination resistors
+5 V signal detection for each HDMI input
Supports color depth processing at 24-bit, 30-bit or 36-bit per pixel
Supports 3D video formats with all structures and all timings up to 2.25 GHz
Supports all Data Island packets
Activity detection on each input, manages output activity and power consumption
Extended mode: re-generate output TMDS waveform removing jitter and skew
Frequency measurement allowing direct reading of format/resolution
Automatic mode for main features:
Automatic Hot Plug Detect (HPD) generation and termination resistors
management
1 page  
NXP Semiconductors
7. Pinning information
7.1 Pinning
TDA19998HL
Smart HDMI 1.4a (4 : 1) switch with auto-adaptive equalizer
1 75
TDA19998
25 51
Fig 2. Pin configuration
001aal396
7.2 Pin description
Table 3. Pin description
Symbol
Pin Type[1] Description
VSS
OUT_C+
1G
2O
ground
HDMI output positive clock channel
OUT_C−
3O
HDMI output negative clock channel
VDDO(3V3)
4
OUT_DDC_CLK 5
P
O
output supply voltage; 3.3 V
DDC-bus clock output; open-drain; 5 V tolerant
OUT_DDC_DAT 6 I/O DDC-bus data input/output; open-drain; 5 V tolerant
VSS
VDDDC(1V8)
RXA_HPD
7G
8P
9O
ground
digital core supply voltage; 1.8 V
HDMI output A Hot Plug Detect; 5 V tolerant
RXA_5V
10 I
input A HDMI +5 V
RXA_DDC_DAT 11 I/O
HDMI input/output A DDC-bus serial data; open-drain; 5 V
tolerant
RXA_DDC_CLK 12 I
HDMI input A DDC-bus serial clock; open-drain; 5 V tolerant
RXA_C−
13 I
HDMI input A negative clock channel
RXA_C+
14 I
HDMI input A positive clock channel
VDDH(3V3)
RXA_D0−
15 P
16 I
HDMI input A supply voltage; 3.3 V
HDMI input A negative data channel 0
RXA_D0+
17 I
HDMI input A positive data channel 0
VSS
RXA_D1−
18 G
19 I
ground
HDMI input A negative data channel 1
RXA_D1+
20 I
HDMI input A positive data channel 1
VDDH(3V3)
RXA_D2−
21 P
22 I
HDMI input A supply voltage; 3.3 V
HDMI input A negative data channel 2
TDA19998HL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 August 2010
© NXP B.V. 2010. All rights reserved.
5 of 26
5 Page 
NXP Semiconductors
TDA19998HL
Smart HDMI 1.4a (4 : 1) switch with auto-adaptive equalizer
Table 4. Power management …continued
Functions
INT_N/MUTE management
Termination resistors
Activity detection
Equalizer (when active)
TMDS buffer extended mode
TMDS output (if active)
Configuration register read/write
Configuration nonvolatile memory download
Configuration nonvolatile memory write
Mode
EDID-only
off
off
off
off
off
off
off
off
off
Power-down
on
off
off
off
off
off
on
on
off
Idle
on
[4]
[4]
[4]
[3]
[4]
on
on
on
Operating
on
[4]
[4]
[4]
[3]
[4]
on
on
on
[1] x = A, B, C or D.
[2] When 5 V is indicated, a +5 V input signal is available on at least one HDMI input and/or pin AUX_5V is powered.
[3] Nonvolatile memory.
[4] Bit state dependent.
[5] x = A, B, C, D or E.
8.13 Power supplies
The termination supply voltage must be 3.3 V ± 5 % with a termination resistance of
50 Ω ± 10 % as defined in the HDMI 1.4a specification.
A dedicated 3.3 V ± 10 % supply (powering interrupt pin INT_N/MUTE) is kept for
compatibility with TDA9996. This pin shall be connected to the rest of 3.3 V supply line.
The 1.8 V supply must also be ±10 %.
A double Power-On Reset (POR) is implemented to manage different delays between
both supply ramp-ups. POR is managed internally without a reset pin. All 1.8 V power
supply pins (VDDDC, VDDH, VDDO) could be connected together (i.e. these pins must be
shorted out).
+5 V from the HDMI connector and AUX_5V pin are used to supply the EDID memory and
the corresponding DDC-bus slave module. To maintain the EDID (volatile memory part)
contents modified by I2C-bus, it is necessary to have +5 V (from HDMI connector or
AUX_5V pin) constantly available.
8.14 I2C-bus
The TDA19998HL allows software programming of its internal registers using the I2C-bus.
The I2C-bus is a separate bus to the DDC-bus, ensuring that I2C-bus programming of the
TDA19998HL’s registers does not influence DDC-bus operation. The TDA19998HL
supports I2C-bus Fast-mode (400 kHz).
8.14.1 I2C-bus protocol
To access registers, the TDA19998HL uses the I2C-bus. The TDA19998HL acts as an
I2C-bus slave device. Pin I2C_SCL is used as the input pin. Both Fast-mode (400 kHz)
and Standard-mode (100 kHz) are supported by the TDA19998HL. The slave I2C-bus
address is shown in Table 5.
TDA19998HL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 August 2010
© NXP B.V. 2010. All rights reserved.
11 of 26
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