|
|
PDF VT82C570M Data sheet ( Hoja de datos )
| Número de pieza | VT82C570M | |
| Descripción | Green Pentium/P54C PCI/ISA System | |
| Fabricantes | VIA | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de VT82C570M (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
VT82C570M
APOLLO MASTER
Green Pentium/P54C
PCI/ISA System
with Plug and Play and
Master Mode PCI-IDE
DATE : June, 1995
VIA TECHNOLOGIES, INC.
1 page  
VIA Technologies, Inc.
VT82C570M
7. Master Mode Enhanced IDE Controller ......................................16
7.1. IDE Drive Interface Configuration .............................................. 16
7.2. Prefetch and Post Write Buffers ................................................17
7.3. Operation Mode Selection ..........................................................17
7.4. Scatter and Gather and Bus Master Operation......................... 18
8. Plug and Play Controller................................................................18
9. ISA Bus Controller..........................................................................19
10. Power Management Unit..............................................................20
10.1. Idle Timers .................................................................................20
10.2. Handling of Secondary Events................................................. 21
10.3. General Purpose and Peripheral Timers................................. 21
10.4. System Management Interrupt ................................................. 21
10.5. Conserve Mode.......................................................................... 22
11. Multi-function X-Bus Peripherals...............................................22
11.1. Scan Logic .................................................................................22
11.2. The XD to SD buffer: .................................................................23
11.3. Multi-clock generator:...............................................................23
11.4. Keyboard controller .................................................................. 24
11.5. Real time clock ..........................................................................24
11.6. General Purpose Chipselect .................................................... 24
11.7. Programmable Output Port ......................................................24
12.Configuration Registers.................................................................24
VT82C575M Pin Description .................................................................................25
VT82C575M Pin Out in Numerical Order ...........................................................30
VT82C575M Pin Diagram......................................................................................31
VT82C576M Pin Description .................................................................................32
VT82C576M Pin Out in Numerical Order ...........................................................34
-ii-
5 Page 
VIA Technologies, Inc.
VT82C570M
The VT82C570M supports the shadowing of the system, video and other BIOS to speed up the
access. The video and system BIOS can also be write-protected and made cacheable. The unused
portion of the DRAM can be relocated to increase the size of the overall system memory. Access cycles
to either E or C segment can be programmed to be an on-board EPROM cycle to allow the combination
of system and video BIOS for an all-in-one system board implementation. The VT82C570M can also
be programmed to recognize write cycles as EPROM cycles to support field upgradability of flash
EPROM BIOS.
The VT82C570M supports 32-bit PCI bus with 64-bit to 32-bit data conversion. Four levels of
post write buffers are included to allow for concurrent CPU and PCI operation. Consecutive CPU
addresses are converted into burst PCI cycles with byte merging capability for optimal CPU to PCI
throughput. A 32-bit fast data link is established between the two VT82C577M data units and the
VT82C576M PCI bus controller so that the address, data and command information for CPU to PCI
bus transactions is contained in the same chip. This arrangement, unique to the VT82C570M chip set is
crucial in achieving zero wait state buffer movement and implementing sophisticated and upgradable
buffer management schemes such as the byte merging. For PCI master operation, four levels of post
write buffers and four levels of prefetch buffers are included for concurrent PCI bus and DRAM/cache
accesses. Snoop Ahead and Snoop Filtering mechanisms are implemented to allow PCI bus master
transfer rates greater than 110MB/s for typical applications. Furthermore, the ISA and IDE bus are
steered through a peer PCI bus so that the slower traffic does not block the normal traffic of the regular
PCI bus. The VT82C570M is PCI 2.1 compliant.
The integrated master mode IDE controller supports a dual channel/four device enhanced IDE bus
with sixteen levels of double-word prefetch and write buffers. The data bus, control signals, write
buffers and prefetch buffers are separated from those of the PCI bus so that performance and electrical
loading are optimized. The command and recovery time of each IDE device can be individually
programmed in units of PCI bus clock to achieve optimal speed of the device up to >22MB/s. Other
features of the IDE controller include interlaced dual channel commands, full scatter and gather
capability, bus master programming interface for ATA controllers SFF-8038 compliant and complete
software driver support.
The VT82C570M provides two plug and play ports for converting non plug and play devices into
plug and play devices on the main board. The configuration mechanism is compliant with the plug and
play BIOS and the Microsoft Windows 95TM operating system.
The integrated power management unit offers the following modes: normal, doze, sleep, suspend
and conserve. To determine the power management mode, the power management unit monitors IO
events, interrupt, DMA and PCI master request signals to detect the status of system activity. Each
event can be turned off or assigned to one of two event classes tracked by an idle timers, a peripheral
timer and a general purpose timer. The system management interrupt (SMI) may be triggered by
multiple sources including time-out of individual timers, occurrence of system activities, external input
and software programming for flexible applications. Clock speed switching (or throttling), IO and
power control are functions performed by the SMI routine. The power management unit is APM 1.1
compliant.
The VT82C577M data buffers separate the CPU/cache and PCI/DRAM bus so that the two busses
may run concurrently. At the CPU side, the CPUs access cache without interfering with the PCI/DRAM
bus unless a cache miss or non-cacheable cycle is encountered, in which case the write buffers with
concurrent write back capability minimize the interface overhead. At the PCI/DRAM side, the PCI
master devices access DRAM without interfering with the CPU/cache data bus unless a snoop hit
occurs.
The VT82C570M is ideal for high performance, high quality, high energy efficient and high
integration desktop and notebook PCI/ISA computer systems.
-5-
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet VT82C570M.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| VT82C570M | Green Pentium/P54C PCI/ISA System | VIA |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |