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PDF HB7121 Data sheet ( Hoja de datos )

Número de pieza HB7121
Descripción CMOS IMAGE SENSOR With 8-bit ADC
Fabricantes Hynix Semiconductor 
Logotipo Hynix Semiconductor Logotipo



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No Preview Available ! HB7121 Hoja de datos, Descripción, Manual

Semiconductor Inc.
System IC SBU
DESCRIPTION
HB7121B
CMOS IMAGE SENSOR
With 8-bit ADC
HB7121B is a highly integrated single chip CMOS B/W image sensor using Hynix 0.5um CMOS process
developed for image application to realize high efficiency photo sensor. The sensor has 414X314 pixels total,
and 400X300 pixels effective. Each pixel is high photo sensitive, small size active pixel element that converts
photons to analog voltage signal. The sensor has three on-chip 8 bit Digital to Analog Convert (DAC) and 414
comparators to digitize the pixel output. The three on-chip 8 bit DAC can be used for independent gain
control. Hynix proprietary on-chip Correlated Double Sampling (CDS) circuit can reduce Fixed Pattern Noise
(FPN) dramatically. The whole 8 bit digital B/W raw data is directly available on the package pins and just a
few control signals are needed for whole chip control, so it is very ease to configure a system using the
sensor.
FEATURES
l 400 x 300 pixels resolution
l Full function control through standard I2C bus
l 8um x 8um square pixel(with Microlens)
l Built-in Automatic Gain Control (AGC)
l High efficiency photo sensors
l 48 pin CLCC
l Integrated 8-bit ADC for direct digital output
l Anti-blooming circuit
l Low power 3.3V operation (5V tolerant I/O)
l Flexible exposure time control
l Integrated pan control and window sizing
l Integrated on-chip timing and drive control
l Clock speed up to 15MHz
l 1/4" optical format
l Programmable frame rate and synchronous format
TECHNICAL SPECIFICATION
FUNCTIONAL BLOCK DIAGRAM
Pixel resolution
Pixel size
Fill factor(without Microlens)
Format
Sensitivity
Supply voltage for analog
Supply voltage for digital
Supply voltage for 5V tolerant input
Power Consumption
Operating temperature
Technology
402x302
8x8um2
30%
CIF
8.0V/luxžsec
3.3V
3.3V
5.0V
TBD@15MHz
0~40 Centigrade
0.5um 3metal CMOS
I2C
Pixel Array
ADC Block
Line Buffer
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA21000601R_1.1
- 1 - 2001 Hynix System IC SBU

1 page




HB7121 pdf
Semiconductor Inc.
System IC SBU
INPUT / OUTPUT AC CHARACTERISTICS (Continue)
ENB Timing
T4
MCLK
ENB
T6
T
T5
T4 : ENB Setup Time : 5[ns]
T5 : ENB Hold Time : 5[ns]
T6 : ENB valid Time : minimum 2 clock
RESET Timing
Must in Valid (active low) state at least 8 MCLK periods
HB7121B
CMOS IMAGE SENSOR
With 8-bit ADC
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. NO patent licenses are implied.
DA21000601R_1.1
- 5 - 2001 Hynix System IC SBU

5 Page





HB7121 arduino
Semiconductor Inc.
System IC SBU
HB7121B
CMOS IMAGE SENSOR
With 8-bit ADC
n Mode B [5:4] : data_type(data types) <default value : 00b>
These bits define output pixel data types. For Correlated Double Sampling(CDS), every the
pixel of image sensor are measured twice, reference and data respectively, and reference
values or data values can be read out through pixel data pins selectively using these control
bits. To remove the noise caused by circuit, i.e. Fixed Pattern Noise, the image sensor
performs the CDS in default value. Three output data types are supported as follows.
Bit Output data type
00 Data level - Reference level
01 Reference level
10 Data level
11 Reserved
n Mode B[3] : hs_out(HSYNC output configuration) <default value : 0b>
This bit offers two types output style about HSYNC signal. HSYNC only mode and HSYNC &
internal clock mode. If the hs_out is set to one, HSYNC output signal is ANDed signal of
internal pixel clock and data valid. Otherwise HSYNC output pin keep data high state during
valid output period. When HSYNC & internal clock mode is set, HSYNC output can be used
as a pixel data output clock.
data valid
pixel clock
MUX
HSYNC
Mode B[3]
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume
any responsibility for use of circuits described. NO patent licenses are implied.
DA21000601R_1.0
- 11 -
2001 Hnix System IC SBU

11 Page







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