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PDF HB54R1G9F2U-A75B Data sheet ( Hoja de datos )
| Número de pieza | HB54R1G9F2U-A75B | |
| Descripción | 1GB Registered DDR SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
1GB Registered DDR SDRAM DIMM
HB54R1G9F2U-A75B/B75B/10B (128M words × 72 bits, 2 Banks)
Description
Features
The HB54R1G9F2U is a 128M × 72 × 2 bank Double
Data Rate (DDR) SDRAM Module, mounted 36 pieces
of 256Mbits DDR SDRAM (HM5425401BTB) sealed in
TCP package, 1 piece of PLL clock driver, 2 pieces of
register driver and 1 piece of serial EEPROM (2k bits
EEPROM) for Presence Detect (PD). Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 2-bit prefetch-pipelined architecture. Data
strobe (DQS) both for read and write are available for
high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. An outline of
the products is 184-pin socket type package (dual lead
out). Therefore, it makes high density mounting
possible without surface mount technology. It provides
common data inputs and outputs. Decoupling
capacitors are mounted beside each TCP on the
module board.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
• 184-pin socket type package (dual lead out)
Outline: 133.35mm (Length) × 30.48mm (Height) ×
4.80mm (Thickness)
Lead pitch: 1.27mm
• 2.5V power supply (VCC/VCCQ)
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 143MHz/133MHz/125MHz (max.)
• Data inputs and outputs are synchronized with DQS
• 4 banks can operate simultaneously and
independently (Component)
• Burst read/write operation
• Programmable burst length: 2, 4, 8
Burst read stop capability
• Programmable burst sequence
Sequential
Interleave
• Start addressing capability
Even and Odd
• Programmable /CAS latency (CL): 3, 3.5
• 8192 refresh cycles: 7.8µs (8192/64ms)
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0192H30 (Ver. 3.0)
Date Published September 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page  
HB54R1G9F2U-A75B/B75B/10B
Serial PD Matrix*1
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08
Memory type
0 0 0 0 0 1 1 1 07
Number of row address
0 0 0 0 1 1 0 1 0D
Number of column address
0 0 0 0 1 0 1 1 0B
Number of DIMM banks
0 0 0 0 0 0 1 0 02
Module data width
0 1 0 0 1 0 0 0 48
Module data width continuation
0 0 0 0 0 0 0 0 00
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04
DDR SDRAM cycle time, CL = X
-A75B
0 1 1 1 0 0 0 0 70
-B75B
0 1 1 1 0 1 0 1 75
-10B
SDRAM access from clock (tAC)
-A75B/B75B
-10B
1 0 0 0 0 0 0 0 80
0 1 1 1 0 1 0 1 75
1 0 0 0 0 0 0 0 80
DIMM configuration type
0 0 0 0 0 0 1 0 02
12 Refresh rate/type
1 0 0 0 0 0 1 0 82
13 Primary SDRAM width
0 0 0 0 0 1 0 0 04
14 Error checking SDRAM width
0 0 0 0 0 1 0 0 04
SDRAM device attributes:
15 Minimum clock delay back-to-back 0 0 0 0 0 0 0 1 01
column access
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0E
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04
18
SDRAM device attributes:
/CAS latency
19
SDRAM device attributes:
/CS latency
0 0 0 0 1 1 0 0 0C
0 0 0 0 0 0 0 1 01
20
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 1 0 02
21 SDRAM module attributes
0 0 1 0 0 1 1 0 26
22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0
Minimum clock cycle time at
23 CLX - 0.5
-A75B
0 1 1 1 0 1 0 1 75
-B75B/10B
1 0 1 0 0 0 0 0 A0
Maximum data access time (tAC) from
24 clock at CLX - 0.5
0 1 1 1 0 1 0 1 75
-A75B/B75B
-10B
1 0 0 0 0 0 0 0 80
25
Minimum clock cycle time at
CLX - 1
0 0 0 0 0 0 0 0 00
26
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00
27 Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50
Comments
128
256 byte
SDRAM DDR
13
11
2
72 bits
0 (+)
SSTL 2.5V
CL = 2.5*5
0.75ns*5
0.8ns*5
ECC
7.8 µs
Self refresh
×4
×4
1 CLK
2, 4, 8
4
2, 2.5
0
1
Registered
± 0.2V
CL = 2*5
0.75ns*5
0.8ns*5
20ns
Data Sheet E0192H30 (Ver. 3.0)
5
5 Page 
HB54R1G9F2U-A75B/B75B/10B
Electrical Specifications
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Notes: 1. Respect to VSS.
Symbol
VT
VCC, VCCQ
IOUT
PT
Topr
Tstg
Value
–1.0 to +4.6
–1.0 to +4.6
50
18
0 to +55
–50 to +100
Unit Note
V1
V1
mA
W
°C
°C
DC Operating Conditions (TA = 0 to +55°C)
Parameter
Symbol
min.
Typ max.
Unit Notes
Supply voltage
VCC, VCCQ 2.3
2.5 2.7
V 1, 2
VSS
0
00
V
Input reference voltage
VREF
1.15
1.25 1.35
V1
Termination voltage
VTT
VREF – 0.04 VREF
VREF + 0.04 V
1
DC Input high voltage
VIH
VREF + 0.18 —
VCCQ + 0.3 V
1, 3
DC Input low voltage
VIL
–0.3
—
VREF – 0.18 V
1, 4
DC Input signal voltage
VIN (dc)
–0.3
—
VCCQ + 0.3 V
5
DC differential input voltage
Ambient illuminance
VSWING (dc) 0.36
—
VCCQ + 0.6 V
6
——
— 100
lx
Notes: 1. All parameters are referred to VSS, when measured.
2. VCCQ must be lower than or equal to VCC.
3. VIH is allowed to exceed VCC up to 4.6V for the period shorter than or equal to 5ns.
4. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
5. VIN (dc) specifies the allowable dc execution of each differential input.
6. VSWING (dc) specifies the input differential voltage required for switching.
Data Sheet E0192H30 (Ver. 3.0)
11
11 Page | ||
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