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PDF HB52RF649DC-B Data sheet ( Hoja de datos )
| Número de pieza | HB52RF649DC-B | |
| Descripción | 512MB Unbuffered SDRAM S.O.DIMM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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DATA SHEET
512MB Unbuffered SDRAM S.O.DIMM
HB52RF649DC-B (64M words × 72 bits, 2 bank)
HB52RD649DC-B (64M words × 72 bits, 2 bank)
Description
The HB52RF649DC, HB52RD649DC are a 64M × 72 ×
2 banks Synchronous Dynamic RAM Small Outline
Dual In-line Memory Module (S.O.DIMM), mounted 18
pieces of 256M bits SDRAM sealed in TCP package
and 1 piece of serial EEPROM (2k bits) for Presence
Detect (PD). An outline of the products is 144-pin Zig
Zag Dual tabs socket type compact and thin package.
Therefore, they make high density mounting possible
without surface mount technology. They provide
common data inputs and outputs. Decoupling
capacitors are mounted beside TCP on the module
board.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Features
• Fully compatible with: JEDEC standard outline 8
bytes S.O.DIMM
• 144-pin Zig Zag Dual tabs socket type (dual lead out)
PCB height: 33.02mm (1.30inch)
Lead pitch: 0.80mm
• 3.3V power supply
• Clock frequency: 133MHz/100MHz (max.)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed /RAS
• 4 Banks can operates simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8
• 2 variations of burst sequence
Sequential
Interleave
• Programmable /CE latency (CL): 2, 3
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• Low self refresh current
: HB52RF649DC-xxBL (L-version)
: HB52RD649DC-xxBL (L-version)
Document No. E0223H30 (Ver. 3.0)
Date Published April 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page  
HB52RF649DC-B, HB52RD649DC-B
Byte No. Function described
SDRAM access from Clock (3rd
26 highest /CE latency)
Undefined
27 Minimum row precharge time
28
Row active to row active min
(-75)
(-A6)
29 /RE to /CE delay min
30
Minimum /RE pulse width
(-75)
(-A6)
31 Density of each bank on module
Address and command signal input
32 setup time
(-75)
(-A6)
Address and command signal input
33 hold time
(-75)
(-A6)
34
Data signal input setup time
(-75)
(-A6)
35
Data signal input hold time
(-75)
(-A6)
36 to 61 Superset information
62 SPD data revision code
63
Checksum for bytes 0 to 62
(-75)
(-A6)
64 Manufacturer’s JEDEC ID code
65 to 71 Manufacturer’s JEDEC ID code
72 Manufacturing location
73 Manufacturer’s part number
74 Manufacturer’s part number
75 Manufacturer’s part number
76 Manufacturer’s part number
77 Manufacturer’s part number
78
Manufacturer’s part number
(-75)
(-A6)
79 Manufacturer’s part number
80 Manufacturer’s part number
81 Manufacturer’s part number
82 Manufacturer’s part number
83 Manufacturer’s part number
84 Manufacturer’s part number
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0 0 0 0 0 0 0 0 00
0 0 0 1 0 1 0 0 14
0 0 0 0 1 1 1 1 0F
0 0 0 1 0 1 0 0 14
0 0 0 1 0 1 0 0 14
0 0 1 0 1 1 0 1 2D
0 0 1 1 0 0 1 0 32
0 1 0 0 0 0 0 0 40
0 0 0 1 0 1 0 1 15
0 0 1 0 0 0 0 0 20
0 0 0 0 1 0 0 0 08
0 0 0 1 0 0 0 0 10
0 0 0 1 0 1 0 1 15
0 0 1 0 0 0 0 0 20
0 0 0 0 1 0 0 0 08
0 0 0 1 0 0 0 0 10
0 0 0 0 0 0 0 0 00
0 0 0 1 0 0 1 0 12
0 1 0 1 1 1 0 1 5D
1 1 0 0 0 1 0 0 C4
0 0 0 0 0 1 1 1 07
0 0 0 0 0 0 0 0 00
× × × × × × × × ××
0 1 0 0 1 0 0 0 48
0 1 0 0 0 0 1 0 42
0 0 1 1 0 1 0 1 35
0 0 1 1 0 0 1 0 32
0 1 0 1 0 0 1 0 52
0 1 0 0 0 1 1 0 46
0 1 0 0 0 1 0 0 44
0 0 1 1 0 1 1 0 36
0 0 1 1 0 1 0 0 34
0 0 1 1 1 0 0 1 39
0 1 0 0 0 1 0 0 44
0 1 0 0 0 0 1 1 43
0 0 1 0 1 1 0 1 2D
Comments
20ns
15ns
20ns
20ns
45ns
50ns
256M byte
1.5ns
2.0ns
0.8ns
1.0ns
1.5ns
2.0ns
0.8ns
1.0ns
Future use
Rev. 1.2B
93
196
HITACHI
*2 (ASCII-8bit code)
H
B
5
2
R
F
D
6
4
9
D
C
Data Sheet E0223H30 (Ver. 3.0)
5
5 Page 
HB52RF649DC-B, HB52RD649DC-B
Notes: 1. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.5V.
2. Access time is measured at 1.5V. Load condition is CL = 50pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
5. tCES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
• Input and output timing reference levels: 1.5V
• Input waveform and output load: See following figures
input
2.4V
2.0V
0.4V 0.8V
I/O
tT tT
Input waveform and output load
CL
Data Sheet E0223H30 (Ver. 3.0)
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HB52RF649DC-B.PDF ] | |
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