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PDF HB52RF648DC-B Data sheet ( Hoja de datos )
| Número de pieza | HB52RF648DC-B | |
| Descripción | 512 MB Unbuffered SDRAM S.O.DIMM 64-Mword 64-bit/ 133/100 MHz Memory Bus/ 2-Bank Module (16 pcs of 32 M 8 components) PC133/100 SDRAM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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HB52RF648DC-B, HB52RD648DC-B
512 MB Unbuffered SDRAM S.O.DIMM
64-Mword × 64-bit, 133/100 MHz Memory Bus, 2-Bank Module
(16 pcs of 32 M × 8 components)
PC133/100 SDRAM
E0083H40 (Ver. 4.0)
Nov. 16, 2001 (K) Japan
Description
The HB52RF648DC, HB52RD648DC are a 32M × 64 × 2 banks Synchronous Dynamic RAM Small Outline
Dual In-line Memory Module (S.O.DIMM), mounted 16 pieces of 256-Mbit SDRAM (HM5225805BTB)
sealed in TCP package and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the
products is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high
density mounting possible without surface mount technology. They provide common data inputs and outputs.
Decoupling capacitors are mounted beside TCP on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would
be electrical defects.
Features
• Fully compatible with: JEDEC standard outline 8-byte S.O.DIMM
• 144-pin Zig Zag Dual tabs socket type (dual lead out)
Outline: 67.60 mm (Length) × 31.75 mm (Height) × 3.80 mm (Thickness)
Lead pitch: 0.80 mm
• 3.3 V power supply
• Clock frequency: 133/100 MHz (max)
• LVTTL interface
• Data bus width: × 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page  
Pin Description
Pin name
A0 to A12
BA0/BA1
DQ0 to DQ63
S0/S1
RE
CE
W
DQMB0 to DQMB7
CK0/CK1
CKE0/CKE1
SDA
SCL
VCC
VSS
NC
HB52RF648DC-B, HB52RD648DC-B
Function
Address input
Row address A0 to A12
Column address A0 to A9
Bank select address
Data-input/output
Chip select
Row address asserted bank enable
Column address asserted
Write enable
Byte input/output mask
Clock input
Clock enable
Data-input/output for serial PD
Clock input for serial PD
Power supply
Ground
No connection
Data Sheet E0083H40
5
5 Page 
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Note: 1. Respect to VSS.
HB52RF648DC-B, HB52RD648DC-B
Symbol
VT
VCC
Iout
PT
Topr
Tstg
Value
–0.5 to VCC + 0.5
(≤ 4.6 (max))
–0.5 to +4.6
50
8.0
0 to +65
–55 to +125
Unit
V
V
mA
W
°C
°C
Note
1
1
DC Operating Conditions (Ta = 0 to +65°C)
Parameter
Symbol
Min
Max
Supply voltage
Input high voltage
Input low voltage
Ambient illuminance
VCC 3.0 3.6
VSS 0 0
VIH 2.0 VCC + 0.3
VIL –0.3 0.8
— — 100
Notes: 1. All voltage referred to VSS
2. The supply voltage with all VCC pins must be on the same level.
3. The supply voltage with all VSS pins must be on the same level.
4. VIH (max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC.
5. VIL (min) = VSS – 2.0 V for pulse width ≤ 3 ns at VSS.
Unit
V
V
V
V
lx
Notes
1, 2
3
1, 4
1, 5
Data Sheet E0083H40
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet HB52RF648DC-B.PDF ] | |
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