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PDF HB52E649E12-B6B Data sheet ( Hoja de datos )
| Número de pieza | HB52E649E12-B6B | |
| Descripción | 512 MB Registered SDRAM DIMM 64-Mword 72-bit/ 100 MHz Memory Bus/ 1-Bank Module (18 pcs of 64 M 4 Components) PC100 SDRAM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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HB52E649E12-A6B/B6B
512 MB Registered SDRAM DIMM
64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module
(18 pcs of 64 M × 4 Components)
PC100 SDRAM
E0020H20 (Ver. 2.0)
Aug. 20, 2001 (K)
Description
The HB52E649E12 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been developed
as an optimized main memory solution for 8-byte processor applications. The HB52E649E12 is a 64M × 72
× 1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit SDRAM
(HM5225405BTT) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1
piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52E649E12 is 168-pin
socket type package (dual lead out). Therefore, the HB52E649E12 makes high density mounting possible
without surface mount technology. The HB52E649E12 provides common data inputs and outputs.
Decoupling capacitors are mounted beside each TSOP on the module board.
Features
• Fully compatible with : JEDEC standard outline 8-byte DIMM
: Intel PCB Reference design (Rev.1.2)
• 168-pin socket type package (dual lead out)
Outline: 133.37 mm (Length) × 43.18 mm (Height) × 4.00 mm (Thickness)
Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
Sequential
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page  
HB52E649E12-A6B/B6B
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0 Number of bytes used by 1 0 0 0 0 0 0 0 80 128
module manufacturer
1 Total SPD memory size
0 0 0 0 1 0 0 0 08
256 byte
2 Memory type
0 0 0 0 0 1 0 0 04
SDRAM
3 Number of row addresses bits 0 0 0 0 1 1 0 1 0D 13
4 Number of column addresses 0 0 0 0 1 0 1 1 0B 11
bits
5 Number of banks
0 0 0 0 0 0 0 1 01
1
6 Module data width
0 1 0 0 1 0 0 0 48
72 bit
7 Module data width (continued) 0 0 0 0 0 0 0 0 00 0 (+)
8 Module interface signal levels 0 0 0 0 0 0 0 1 01 LVTTL
9 SDRAM cycle time
(highest CE latency)
10 ns
1 0 1 0 0 0 0 0 A0
CL = 3
10
SDRAM access from Clock
0 1 1 0 0 0 0 0 60
(highest CE latency)
6 ns
*7
11 Module configuration type
0 0 0 0 0 0 1 0 02
ECC
12 Refresh rate/type
1 0 0 0 0 0 1 0 82
Normal
(7.8125 µs)
Self refresh
13 SDRAM width
0 0 0 0 0 1 0 0 04
64M × 4
14 Error checking SDRAM width 0 0 0 0 0 1 0 0 04
×4
15 SDRAM device attributes:
0 0 0 0 0 0 0 1 01
minimum clock delay for back-to-
back random column addresses
1 CLK
16 SDRAM device attributes:
Burst lengths supported
0 0 0 0 1 1 1 1 0F
1, 2, 4, 8
17 SDRAM device attributes:
0 0 0 0 0 1 0 0 04
number of banks on SDRAM
device
4
18 SDRAM device attributes:
CE latency
(-A6B)
0 0 0 0 0 1 1 0 06
2/3
(-B6B)
0 0 0 0 0 1 0 0 04
3
19 SDRAM device attributes:
S latency
0 0 0 0 0 0 0 1 01
0
20 SDRAM device attributes:
W latency
0 0 0 0 0 0 0 1 01
0
21 SDRAM device attributes
0 0 0 1 1 1 1 1 1F
Registered
Data Sheet E0020H20
5
5 Page 
HB52E649E12-A6B/B6B
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
Max
Unit
Notes
Input capacitance (Address)
CI1 15 pF 1, 2, 4
Input capacitance (RE, CE, W)
CI2 15 pF 1, 2, 4
Input capacitance (CKE)
CI3 23 pF 1, 2, 4
Input capacitance (S)
CI4 15 pF 1, 2, 4
Input capacitance (CK)
CI5 40 pF 1, 2, 4
Input capacitance (DQMB)
CI6 15 pF 1, 2, 4
Input/Output capacitance (DQ)
CI/O1
15
pF
1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = VIH to disable Data-out.
4. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
System clock cycle time
(CE latency = 3)
(CE latency = 4)
CK high pulse width
CK low pulse width
Access time from CK
(CE latency = 3)
(CE latency = 4)
Data-out hold time
CK to Data-out low impedance
CK to Data-out high impedance
Data-in setup time
Data in hold time
Address setup time
Address hold time
CKE setup time
CKE setup time for power down exit
CKE hold time
Symbol
t CK
PC100
Symbol
Tclk
HB52E649E12
-A6B/B6B
Min Max
10 —
tCK Tclk 10
tCKH Tch 4
tCKL Tcl 4
tAC Tac —
—
—
—
6.9
t AC
t OH
t LZ
t HZ
t DS
t DH
t AS
t AH
t CES
t CESP
t CEH
Tac
Toh
Tsi
Thi
Tsi
Thi
Tsi
Tpde
Thi
—
2.1
1.1
—
2.9
1.9
2.6
1.6
2.6
2.6
1.6
6.9
—
—
6.9
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1, 5
1, 5
1
1
Data Sheet E0020H20
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HB52E649E12-B6B.PDF ] | |
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