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PDF SAM9G15 Data sheet ( Hoja de datos )
| Número de pieza | SAM9G15 | |
| Descripción | AT91SAM ARM-based Embbedded MPU | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT91SAM ARM-based Embbedded MPU
SAM9G15
DATASHEET
Description
The SAM9G15, based on the ARM926EJ-S™ processor, runs at 400 MHz and
integrates a rich set of peripherals to support embedded industrial applications that
require advanced user interfaces and high-speed communication.
The SAM9G15 features a graphics LCD controller with 4-layer overlay and 2D
acceleration (picture-in-picture, alpha-blending, scaling, rotation, color conversion),
and a 10-bit ADC that supports 4/5-wire resistive touchscreen panels. Multiple
communication interfaces include a soft modem supporting exclusively the Conexant
SmartDAA line driver, HS USB Host and Device and FS USB Host with dedicated on-
chip transceivers, two HS SDCard/SDIO/MMC interfaces, USARTs, SPIs, I2S and
TWIs.
The 10-layer bus matrix coupled with multiple DMA channels ensures uninterrupted
data transfers with minimal processor overhead.
The External Bus Interface incorporates controllers offering support for 4-bank and 8-
bank DDR2/LPDDR, SDRAM/LPSDRAM, static memories, as well as specific circuitry
for MLC/SLC NAND Flash with integrated ECC up to 24 bits.
The SAM9G15 is available in a 217-ball BGA package with 0.8 mm ball pitch.
11052E–ATARM–06-Feb-13
1 page  
Table 3-1. Signal Description List (Continued)
Signal Name
Function
External Bus Interface - EBI
D0-D15
Data Bus
D16-D31
Data Bus
A0-A25
Address Bus
NWAIT
External Wait Signal
Static Memory Controller - SMC
NCS0-NCS5
Chip Select Lines
NWR0-NWR3
Write Signal
NRD
Read Signal
NWE
Write Enable
NBS0-NBS3
Byte Mask Signal
NAND Flash Support
NFD0-NFD16
NAND Flash I/O
NANDCS
NAND Flash Chip Select
NANDOE
NAND Flash Output Enable
NANDWE
NAND Flash Write Enable
DDR2/SDRAM/LPDDR Controller
SDCK,#SDCK
DDR2/SDRAM Differential Clock
SDCKE
DDR2/SDRAM Clock Enable
SDCS
DDR2/SDRAM Controller Chip Select
BA[0..2]
Bank Select
SDWE
DDR2/SDRAM Write Enable
RAS-CAS
Row and Column Signal
SDA10
SDRAM Address 10 Line
DQS[0..1]
Data Strobe
DQM[0..3]
Write Data Mask
High Speed MultiMedia Card Interface - HSMCI0-1
MCI0_CK, MCI1_CK
Multimedia Card Clock
MCI0_CDA, MCI1_CDA
Multimedia Card Slot Command
MCI0_DA0-MCI0_DA3
Multimedia Card 0 Slot A Data
MCI1_DA0-MCI1_DA3
Multimedia Card 1 Slot A Data
Type
I/O
I/O
Output
Input
Output
Output
Output
Output
Output
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O
Output
I/O
I/O
I/O
I/O
Active Level
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
SAM9G15 [DATASHEET]
11052E–ATARM–06-Feb-13
5
5 Page 
4.3 217-ball BGA Package Pinout
Table 4-3. Pin Description BGA217
Primary
Ball Power Rail I/O Type
L3 VDDIOP0
GPIO
P1 VDDIOP0
GPIO
L4 VDDIOP0
GPIO
N4 VDDIOP0
GPIO
T3 VDDIOP0
GPIO
R1 VDDIOP0
GPIO
R4 VDDIOP0
GPIO
R3 VDDIOP0
GPIO
P4 VDDIOP0
GPIO
U3 VDDIOP0
GPIO
T1 VDDIOP0
GPIO
U1 VDDIOP0
GPIO
T2 VDDIOP0
GPIO
T4 VDDIOP0 GPIO_CLK
U2 VDDIOP0
GPIO
U4 VDDIOP0
GPIO
P5 VDDIOP0
GPIO
R5 VDDIOP0 GPIO_CLK
U5 VDDIOP0
GPIO
T5 VDDIOP0
GPIO
U6 VDDIOP0
GPIO
T6 VDDIOP0
GPIO
R6 VDDIOP0
GPIO
U7 VDDIOP0 GPIO_CLK
T7 VDDIOP0
GPIO
T8 VDDIOP0
GPIO
R7 VDDIOP0
GPIO
P8 VDDIOP0
GPIO
U8 VDDIOP0
GPIO
R9 VDDIOP0
GPIO
R8 VDDIOP0
GPIO
U9 VDDIOP0
GPIO
D3 VDDANA
GPIO
D4 VDDANA
GPIO
D2 VDDANA
GPIO
E4 VDDANA
GPIO
D1 VDDANA GPIO_CLK
E3 VDDANA
GPIO
Signal
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PB0
PB1
PB2
PB3
PB4
PB5
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Alternate
PIO Peripheral A
PIO Peripheral B
Signal
Dir Signal Dir Signal Dir
TXD0
O SPI1_NPCS1 O
RXD0
I SPI0_NPCS2 O
RTS0
O MCI1_DA1 I/O
CTS0
I MCI1_DA2 I/O
SCK0
I/O MCI1_DA3 I/O
TXD1
O
RXD1
I
TXD2
O SPI0_NPCS1 O
RXD2
I SPI1_NPCS0 I/O
DRXD
I
DTXD
O
SPI0_MISO I/O MCI1_DA0 I/O
SPI0_MOSI I/O MCI1_CDA I/O
SPI0_SPCK I/O MCI1_CK
I/O
SPI0_NPCS0 I/O
MCI0_DA0 I/O
MCI0_CDA I/O
MCI0_CK I/O
MCI0_DA1 I/O
MCI0_DA2 I/O
MCI0_DA3 I/O
TIOA0
I/O SPI1_MISO I/O
TIOA1
I/O SPI1_MOSI I/O
TIOA2
I/O SPI1_SPCK I/O
TCLK0
I
TK I/O
TCLK1
I
TF I/O
TCLK2
I
TD
O
TIOB0
I/O
RD
I
TIOB1
I/O
RK
I/O
TIOB2
I/O
RF
I/O
TWD0
I/O SPI1_NPCS3 O
TWCK0
O SPI1_NPCS2 O
RTS2
O
CTS2
I
SCK2
I/O
SPI0_NPCS3 O
TWD2
I/O
TWCK2
O
PIO Peripheral C Reset State
Signal
Signal, Dir,
Dir PU, PD, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAM9G15 [DATASHEET]
11052E–ATARM–06-Feb-13
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAM9G15.PDF ] | |
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