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CED61A3 fiches techniques PDF

Chino-Excel Technology - N-Channel Logic Level Enhancement Mode Field Effect Transistor

Numéro de référence CED61A3
Description N-Channel Logic Level Enhancement Mode Field Effect Transistor
Fabricant Chino-Excel Technology 
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CED61A3 fiche technique
CED61A3/CEU61A3
Jan. 2003
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
30V , 40A , RDS(ON)=13.5m@VGS=10V.
6 RDS(ON)=20m @VGS=4.5V.
Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-251 & TO-252 package.
D
G
G
S
CEU SERIES
TO-252AA(D-PAK)
G
DS
CED SERIES
TO-251(l-PAK)
D
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
-Pulsed
Drain-Source Diode Forward Current
Maximum Power Dissipation @Tc=25 C
Derate above 25 C
Operating and Storage Temperature Range
Symbol
VDS
VGS
ID
IDM
IS
PD
TJ, TSTG
Limit
30
Ć20
40
120
40
50
0.4
-55 to 150
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
RįJC
RįJA
6-62
2.5
50
C/W
C/W

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