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PDF IP4284CZ10-TT Data sheet ( Hoja de datos )
| Número de pieza | IP4284CZ10-TT | |
| Descripción | ESD protection | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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IP4284CZ10-TBR;
IP4284CZ10-TT
ESD protection for ultra high-speed interfaces
Rev. 3 — 19 May 2011
Product data sheet
1. Product profile
1.1 General description
The devices are designed to protect high-speed interfaces such as High-Definition
Multimedia Interface (HDMI), DisplayPort, SuperSpeed USB, external Serial Advanced
Technology Attachment (eSATA) and Low Voltage Differential Signaling (LVDS) interfaces
against ElectroStatic Discharge (ESD).
The devices include high-level ESD protection diodes for ultra high-speed signal lines and
are available in two package variants: XSON10 and TSSOP10.
All signal lines are protected by a special diode configuration offering ultra low line
capacitance of only 0.5 pF. These diodes provide protection to downstream components
from ESD voltages up to ±8 kV contact according to IEC 61000-4-2, level 4.
1.2 Features and benefits
Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen
and antimony (Dark Green compliant)
System ESD protection for USB 2.0 and USB SuperSpeed 3.0, HDMI 1.3 and
HDMI 1.4, DisplayPort, eSATA and LVDS
All signal lines with integrated rail-to-rail clamping diodes for downstream
ESD protection of ±8 kV according to IEC 61000-4-2, level 4
Matched 0.5 mm trace spacing
Signal lines with ≤ 0.05 pF matching capacitance between signal pairs
Line capacitance of only 0.5 pF for each channel
4-channel, XSON10 or TSSOP10 Pb-free package
Design-friendly ’pass-thru’ signal routing
1.3 Applications
The devices are designed for high-speed receiver and transmitter port protection:
TVs, monitors
DVD recorders and players
Notebooks, mother boards, graphic cards and ports
Set-top boxes and game consoles
1 page  
NXP Semiconductors
IP4284CZ10-TBR/TT
ESD protection for ultra high-speed interfaces
5 Gbit/s; USB 3.0 CP0 pattern
Fig 3. Eye diagram using reference PCB
018aaa004
018aaa005
5 Gbit/s; USB 3.0 CP0 pattern
Fig 4. Typical eye diagram for IP4284CZ10
0.4
Cd
(pF)
0.2
018aaa006
(1)
0.0
(2)
−0.2
−0.4
−0.5
1.5
3.5 5.5
Vbias (V)
(1) Pin 2
(2) Pin 1
Deviation from typical capacitance normalized at Vbias = 2.5 V
Fig 5. Line capacitance as a function of bias voltage; typical values
IP4284CZ10-TBR_TT
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 19 May 2011
© NXP B.V. 2011. All rights reserved.
5 of 17
5 Page 
NXP Semiconductors
9. Soldering
IP4284CZ10-TBR/TT
ESD protection for ultra high-speed interfaces
Footprint information for reflow soldering of XSON10 package
SOT1176-1
Hx
Hy Ay By
C
0.05
D P 0.05
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
solder resist
Dimensions in mm
P Ay By
C
0.5 1.25 0.3 0.475
D
0.2
Hx
2.45
Hy
1.5
Remark:
Stencil of 75 μm is recommended.
A stencil of 75 μm gives an aspect ratio of 0.77
With a stencil of 100 μm one will obtain an aspect ratio of 0.58
Reflow soldering is the only recommended soldering method.
Fig 14. Reflow soldering footprint SOT1176-1 (XSON10)
sot1176-1_fr
IP4284CZ10-TBR_TT
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 19 May 2011
© NXP B.V. 2011. All rights reserved.
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