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PDF TDA7703RTR Data sheet ( Hoja de datos )
| Número de pieza | TDA7703RTR | |
| Descripción | Highly integrated tuner | |
| Fabricantes | STMicroelectronics | |
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TDA7703R
Highly integrated tuner for AM/FM car radio
Features
■ Fully integrated VCO for world tuning
■ High performance PLL for fast RDS system
■ AM/FM mixers with high image rejection
■ Integrated AM-LNA and AM-PINDIODE
■ Automatic self alignment for image rejection
■ Digital IF signal processing, high performance
and drift-free
■ Integrated IF-filters with high selectivity, high
dynamic range and FM adaptive bandwidth
control
■ RDS demodulation with group and block
synchronization
■ High performance stereodecoder with
noiseblanker
■ I2C bus controlled
■ Single 5 V supply
■ LQFP44 package
Description
The TDA7703R highly integrated tuner (HIT44) is
part of a family of tuners for carradio applications.
LQFP44
It contains mixers and IF amplifiers for AM and
FM, fully integrated VCO and PLL synthesizer,
IF-processing including adaptive bandwidth
control (FM), stereo decoder and RDS decoder
on a single chip.
The utilization of digital signal processing results
in numerous advantages against today's tuners:
– Very low number of external components
– Very small space occupation and easy
application
– Very high selectivity due to digital filters
– High flexibility by software control
– Automatic image rejection alignment.
Table 1. Device summary
Order code
TDA7703R
TDA7703RTR
Package
LQFP44 (10x10x1.4mm)
LQFP44 (10x10x1.4mm)
Packing
Tray
Tape and reel
January 2010
Rev 1.2
1/32
www.st.com
1
1 page  
TDA7703R
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I2C "write" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I2C "read" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I2C bus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FM input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AM MW input set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AM LW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LQFP44 (10x10x1.4mm) mechanical data and package dimensions. . . . . . . . . . . . . . . . . 30
Rev 1.2
5/32
5 Page 
TDA7703R
Function description
2.12
IO interface pins
The TDA7703R has the following IO pins:
SDA
pin 26 serial communication with µP
SCL pin 27 serial communication with µP
RDSINT pin 29 RDS interrupt line towards µP
RSTN pin 30 reset pin driven by µP
All the inputs are voltage-tolerant up to 3.5 V . The outputs can drive currents up to 0.5 mA
from the internal 3.3 V supply line.
2.13
Serial interface
The device is controlled with a standard I2C bus interface.
Through the serial bus the processing parameters can be modifed and the signal quality
parameters and the RDS information can be read out.
The operation of the device is handled through high level commands sent by the main car-
radio µP through the serial interface, which allow to simplify the operations carried out in the
main µP. The high level commands include among others:
● set frequency (which allows to avoid computing the PLL divider factors);
● start seek (the seek operation can be carried out by the TDA7703R in a completely
autonomous fashion);
● RDS seek/search (jumps to AF and quality measurements are automatically
sequenced).
The serial bus communication configuration is set by forcing pin 29 (RDSINT) to ground
when the RSTN line transitions from low to high (when RSTN is low, the IC is in reset mode).
The voltage level forced to pin 29 must be released to start the system operation a suitable
time after the RSTN line has gone high. The I2C address is 0xC2 (write) / 0xC3 (read).
The status of pin 29 during the reset phase can be set to low by not forcing any voltage on it
from outside, as a 50 kΩ internal pull-down resistors is present.
To make sure the boot mode is correctly latched up at start-up, it is advisable to keep the
RSTN line low until the IC supply pins have reached their steady state, and then for an
additional time Treset (see Section 3.4.6).
I2C requires two signals: clock (SCL) and data (SDA - bidirectional). The protocol requires
an acknowledge after any 8-bit transmission.
A "write" communication example is shown in the figure below, for an unspecified number of
data bytes (see the relevant technical documentation for frame structure description):
Figure 3. I2C "write" sequence
SDA
SCL
START
a7 a6 …
clk1 clk2
…
address
a0
clk8
clk9
ACK
d7
clk1
d6 …
clk2 …
data
d0
clk8
clk9
ACK
STOP
Rev 1.2
11/32
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