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PDF ADuM7223 Data sheet ( Hoja de datos )
| Número de pieza | ADuM7223 | |
| Descripción | Isolated Precision Half-Bridge Driver | |
| Fabricantes | Analog Devices | |
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Data Sheet
Isolated Precision Half-Bridge
Driver, 4.0 A Output
ADuM7223
FEATURES
4.0 A peak output current
Working voltage
High-side or low-side relative to input: 565 V peak
High-side to low-side differential: 700 V peak
High frequency operation: 1 MHz maximum
Precise timing characteristics
64 ns maximum propagation delay
8.5 ns maximum channel-to-channel matching
3.0 V to 5.5 V input voltage
4.5 V to 18 V output drive
UVLO supply at 2.8 V VDD1
A Version UVLO, VDDA and VDDB (VDD2) at 4.1 V
B Version UVLO, VDDA and VDDB at 6.9 V
C Version UVLO, VDDA and VDDB at 10.5 V
CMOS input logic levels
High common-mode transient immunity: >25 kV/μs
High junction temperature operation: 125°C
Default low output
5 mm × 5 mm, 13-terminal LGA
APPLICATIONS
Switching power supplies
Isolated IGBT/MOSFET gate drives
Industrial inverters
GENERAL DESCRIPTION
The ADuM7223 is a 4.0 A isolated, half-bridge gate driver that
employs Analog Devices, Inc., iCoupler® technology to provide
independent and isolated high-side and low-side outputs.
Combining high speed CMOS and monolithic transformer
technology, these isolation components provide outstanding
performance characteristics superior to alternatives such as the
combination of pulse transformers and non-isolated gate
drivers. By integrating the isolator and driver in a single
package, propagation delay is a maximum of only 64 ns, and the
propagation skew from channel to channel is a maximum of
only 12 ns at 12 V.
The ADuM7223 provides two independent isolation channels.
The ADuM7223 operates with an input supply ranging from 3.0 V
to 5.5 V, providing compatibility with lower voltage systems.
The outputs operate in a wide range from 4.5 V to 18 V with
three output voltage versions available. The 5 mm × 5 mm, LGA
package provides 565 V operating voltage from input to output
and 700 V from output to output.
In comparison to gate drivers employing high voltage level
translation methodologies, this gate driver offers the benefit of
true, galvanic isolation between the input and each output. As a
result, this gate driver provides reliable control over the
switching characteristics of IGBT/MOSFET configurations over
a wide range of positive or negative switching voltages.
FUNCTIONAL BLOCK DIAGRAM
GND1 1
ADuM7223
13 VDDA
VIA 2
ENCODE
DECODE
12 VOA
VIB 3
11 GNDA
NC 4
DISABLE 5
NC 6
VDD1 7
ENCODE
DECODE
10 VDDB
9 VOB
8 GNDB
NC = NO CONNECT
Figure 1.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADuM7223
Parameter
THERMAL SHUTDOWN TEMPERATURES
Junction Temperature Shutdown Rising Edge
Junction Temperature Shutdown Falling Edge
SWITCHING SPECIFICATIONS
Pulse Width2
Maximum Data Rate3
Propagation Delay4
ADuM7223A
Propagation Delay Skew5
Channel-to-Channel Matching6
VDD2 = 12 V
VDD2 = 4.5 V
Output Rise/Fall Time (10% to 90%)
Dynamic Input Supply Current per Channel
Dynamic Output Supply Current per Channel
Refresh Rate
Symbol
TJR
TJF
PW
tDHL, tDLH
tPSK
tPSKCD
tPSKCD
tR/tF
IDDI (D)
IDDO (D)
fr
Min
50
1
25
28
1
Typ Max
150
140
44 64
49 71
12
1 8.5
1 8.5
12 24
0.05
1.65
1.1
Unit Test Conditions/Comments
°C
°C
ns
MHz
ns
ns
ns
See Figure 16
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 4.5 V
CL = 2 nF, VDD2 = 12 V
ns
ns
ns
mA/Mbps
mA/Mbps
Mbps
CL = 2 nF
CL = 2 nF; A-Grade Only
CL = 2 nF, VDD2 = 12 V
VDD2 = 12 V
VDD2 = 12 V
VDD2 = 12 V
1 Short-circuit duration less than 1 µs. Average power must conform to the limit shown under the Absolute Maximum Ratings.
2 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
4 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is
measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 16 for waveforms of propagation delay
parameters.
5 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 16 for waveforms of propagation delay parameters.
6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
Rev. A | Page 5 of 16
5 Page 
Data Sheet
ADuM7223
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM7223 digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
required at the input and output supply pins. Use a small
ceramic capacitor with a value between 0.01 µF and 0.1 µF to
provide a good high frequency bypass. On the output power
supply pins, VDDA or VDDB, it is recommended to add a 10 µF
capacitor in parallel to provide the charge required to drive the
gate capacitance at the ADuM7223 outputs. Lower values of
decoupling can be used provided the designer ensures that
voltage drops during switching transients are acceptable. The
required decoupling is a function of the gate capacitance being
driven versus the acceptable voltage drop. On the output supply
pins, avoid bypass capacitor use of vias, or employ multiple vias
to reduce the inductance in the bypassing. The total lead length
between both ends of the smaller capacitor and the input or
output power supply pin must not exceed 20 mm for best
performance. For best performance, place bypass capacitors as
near to the device as possible.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation
delay to a logic high output. The ADuM7223 specifies tDLH as
the time between the rising input high logic threshold, VIH, to
the output rising 10% threshold (see Figure 16). Likewise, the
falling propagation delay, tDHL, is defined as the time between
the input falling logic low threshold, VIL, and the output falling
90% threshold. The rise and fall times are dependent on the
loading conditions and are not included in the propagation
delay, as is the industry standard for gate drivers.
90%
OUTPUT
10%
INPUT
VIH
VIL
tDLH
tR
tDHL
tF
Figure 16. Propagation Delay Parameters
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM7223 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM7223
devices operating under the same conditions.
THERMAL LIMITATIONS AND SWITCH LOAD
CHARACTERISTICS
For isolated gate drivers, the necessary separation between the
input and output circuits prevents the use of a single thermal
pad beneath the device, and heat is, therefore, dissipated mainly
through the package pins.
Power dissipation within the device is primarily driven by the
effective load capacitance being driven, switching frequency,
operating voltage, and external series resistance. Power
dissipation within each channel can be calculated by
( )PDISSs = CEFF × VDDA/B
2
×
f SW
RDSON
RDSON + RGATE
where:
CEFF is the effective capacitance of the load.
VDDA/B is the secondary side voltage.
fSW is the switching frequency.
RDSON is the internal resistance of the ADuM7223 (ROA, ROB).
RGATE is the external gate resistor.
To find temperature rise above ambient temperature, multiply
total power dissipation by the θJA, which is then added to the
ambient temperature to find the approximate internal junction
temperature of the ADuM7223.
Each of the ADuM7223 isolator outputs have a thermal
shutdown protection function. This function sets an output to a
logic low level when the rising junction temperature typically
reaches 150°C and turns back on after the junction temperature has
fallen from the shutdown value by about 10°C.
OUTPUT LOAD CHARACTERISTICS
The ADuM7223 output signals depend on the characteristics of
the output load, which is typically an N-channel MOSFET. The
driver output response to an N-channel MOSFET load can be
modeled with a switch output resistance (RSW), an inductance
due to the PCB trace (LTRACE), a series gate resistor (RGATE), and a
gate to source capacitance (CGS), as shown in Figure 17.
RSW is the switch resistance of the internal ADuM7223 driver
output (1.1 Ω typical for turn-on and 0.6 Ω for turn-off). RGATE
is the intrinsic gate resistance of the MOSFET and any external
series resistance. A MOSFET that requires a 4 A gate driver has
a typical intrinsic gate resistance of about 1 Ω and a gate-to-
source capacitance (CGS) of between 2 nF and 10 nF. LTRACE is
the inductance of the PCB trace, typically a value of 5 nH or less
for a well-designed layout with a very short and wide connection
from the ADuM7223 output to the gate of the MOSFET.
Rev. A | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADuM7223.PDF ] | |
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