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HCTS132HMSR fiches techniques PDF

Intersil Corporation - Radiation Hardened Quad 2-Input NAND Schmitt Trigger

Numéro de référence HCTS132HMSR
Description Radiation Hardened Quad 2-Input NAND Schmitt Trigger
Fabricant Intersil Corporation 
Logo Intersil Corporation 





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HCTS132HMSR fiche technique
HCTS132MS
August 1995
Radiation Hardened
Quad 2-Input NAND Schmitt Trigger
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii 5µA at VOL, VOH
Description
The Intersil HCTS132MS is a Radiation Hardened Quad 2-Input
NAND Schmitt Trigger inputs. A high on both inputs forces the
output to a Low state.
The HCTS132MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
A1
B1
Y1
A2
B2
Y2
GND
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
VCC
B4
A4
Y4
B3
A3
Y3
The HCTS132MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
TRUTH TABLE
INPUTS
An Bn
OUTPUTS
Yn
PART
TEMPERATURE SCREENING
L LH
NUMBER
RANGE
LEVEL
PACKAGE
L
H
H
HCTS132DMSR -55oC to +125oC Intersil Class
S Equivalent
HCTS132KMSR -55oC to +125oC Intersil Class
S Equivalent
HCTS132D/
Sample
HCTS132K/
Sample
+25oC
+25oC
Sample
Sample
HCTS132HMSR
+25oC
Die
14 Lead SBDIP
14 Lead
Ceramic
Flatpack
14 Lead SBDIP
14 Lead
Ceramic
Flatpack
Die
HLH
HH L
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
nA
(1, 4, 9, 12)
nO
(2, 5, 10, 13)
nY
(3, 6, 8, 11)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
500
Spec Number 518604
File Number 3062.1

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