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Intersil Corporation - Radiation Hardened Quad 2-Input NOR Gate

Numéro de référence HCTS02KMSR
Description Radiation Hardened Quad 2-Input NOR Gate
Fabricant Intersil Corporation 
Logo Intersil Corporation 





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HCTS02KMSR fiche technique
HCTS02MS
August 1995
Radiation Hardened
Quad 2-Input NOR Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD(Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 Rads (Si)/s
• Dose Rate Upset >1010 RAD(Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii 5µA at VOL, VOH
Description
The Intersil HCTS02MS is a Radiation Hardened Quad 2-Input
NOR Gate. A low on both inputs forces the output to a High state.
The HCTS02MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
Y1
A1
B1
Y2
A2
B2
GND
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
Y1 1
A1 2
B1 3
Y2 4
A2 5
B2 6
GND 7
14 VCC
13 Y4
12 B4
11 A4
10 Y3
9 B3
8 A3
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
VCC
Y4
B4
A4
Y3
B3
A3
The HCTS02MS is supplied in a 14 lead Ceramic Flatpack Pack-
age (K suffix) or a 14 lead SBDIP Package (D suffix).
TRUTH TABLE
INPUTS
OUTPUTS
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCTS02DMSR -55oC to +125oC Intersil Class 14 Lead SBDIP
S Equivalent
HCTS02KMSR -55oC to +125oC Intersil Class 14 Lead Ceramic
S Equivalent Flatpack
HCTS02D/
Sample
+25oC
Sample
14 Lead SBDIP
HCTS02K/
Sample
+25oC
Sample
14 Lead Ceramic
Flatpack
HCTS02HMSR
+25oC
Die
Die
An Bn Yn
L LH
LHL
HL L
HH L
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
An
(2, 5, 8, 11)
Bn
(3, 6, 9, 12)
Yn
(1, 4, 10, 13)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518841
File Number 2137.2

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