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PDF HCTS00K Data sheet ( Hoja de datos )
| Número de pieza | HCTS00K | |
| Descripción | Radiation Hardened Quad 2-Input NAND Gate | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HCTS00MS
August 1995
Radiation Hardened
Quad 2-Input NAND Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10-9 Errors/Gate Day (Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• CMOS Input Compatibility Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS00MS is a Radiation Hardened Quad 2-Input
NAND Gate. A high on both inputs forces the output to a Low
state.
The HCTS00MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS00MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCTS00DMSR -55oC to +125oC Intersil Class 14 Lead SBDIP
S Equivalent
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP3-F14
TOP VIEW
A1
B1
Y1
A2
B2
Y2
GND
1 14
2 13
3 12
4 11
5 10
69
78
VCC
B4
A4
Y4
B3
A3
Y3
TRUTH TABLE
INPUTS
OUTPUTS
An Bn Yn
L LH
L HH
HLH
HH L
NOTE: L = Logic Level Low, H = Logic level High
HCTS00KMSR -55oC to +125oC Intersil Class
S Equivalent
HCTS00D/
Sample
+25oC
Sample
HCTS00K/
Sample
+25oC
Sample
HCTS00HMSR
+25oC
Die
14 Lead Ceramic
Flatpack
14 Lead SBDIP
14 Lead Ceramic
Flatpack
Die
Functional Diagram
An
(1, 4, 9, 12)
Bn
(2, 5, 10, 13)
Yn
(3, 6, 8, 11)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
370
Spec Number 518774
File Number 2139.2
1 page  
Specifications HCTS00MS
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V
50kHz
25kHz
STATIC BURN-IN I TEST CONDITIONS (Note 1)
3, 6, 8, 11
1, 2, 4, 5, 7, 9, 10, 12,
13
-
14 - -
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
3, 6, 8, 11
7
-
1, 2, 4, 5, 9, 10, 12,
-
13, 14
-
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)
-
7
3, 6, 8, 11
14
1, 2, 4, 5, 9, 10,
-
12, 13
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% static burn-in.
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
3, 6, 8, 11 7 1, 2, 4, 5, 9, 10, 12, 13, 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5%. Group E, Subgroup 2,
sample size is 4 dice/wafer, 0 failures.
Spec Number 518774
374
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HCTS00K.PDF ] | |
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