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PDF HCS512-SN Data sheet ( Hoja de datos )
| Número de pieza | HCS512-SN | |
| Descripción | KEELOQ CODE HOPPING DECODER | |
| Fabricantes | Microchip Technology | |
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M
HCS512
Code Hopping Decoder
FEATURES
Security
• Secure storage of Manufacturer’s Code
• Secure storage of transmitter’s keys
• Up to four transmitters can be learned
• KEELOQ code hopping technology
• Normal and secure learning mechanisms
Operating
• 3.0V – 6.0V operation
• 4 MHz RC oscillator
• Learning indication on LRNOUT
• Auto baud rate detection
• Power saving sleep mode
Other
• Stand alone decoder
• On-chip EEPROM for transmitter storage
• Four binary function outputs–15 functions
• 18-pin DIP/SOIC package
Typical Applications
• Automotive remote entry systems
• Automotive alarm systems
• Automotive immobilizers
• Gate and garage openers
• Electronic door locks
• Identity tokens
• Burglar alarm systems
Compatible Encoders
• HCS200, HCS300, HCS301, HCS360, HCS361
• NTQ106
DESCRIPTION
The Microchip Technology Inc. HCS512 is a code hop-
ping decoder designed for secure Remote Keyless
Entry (RKE) systems. The HCS512 utilizes the pat-
ented KEELOQ code hopping system and high security
learning mechanisms to make this a canned solution
when used with the HCS encoders to implement a uni-
directional remote keyless entry system.
PACKAGE TYPE
PDIP, SOIC
LRNIN
LRNOUT
NC
MCLR
GND
S0
S1
S2
S3
1
2
3
4
5
6
7
8
9
18 RFIN
17 NC
16 OSCIN
15 OSCOUT
14 VDD
13 DATA
12 CLK
11 SLEEP
10 VLOW
BLOCK DIAGRAM
RFIN
67-Bit Reception Register
EEPROM
CONTROL
OSCIN OSCILLATOR
DECRYPTOR
DATA
CLK
LRNIN
SEL
MCLR
SLEEP
OUTPUT
CONTROL
S0 S1 S2 S3 VLOW LRNOUT
The Manufacturer’s Code, transmitter keys, and syn-
chronization information are stored in protected on-chip
EEPROM. The HCS512 uses the DATA and CLK inputs
to load the Manufacturer’s Code which cannot be read
out of the device.
The HCS512 operates over a wide voltage range of
3.0 volts to 6.0 volts. The decoder employs automatic
baud rate detection which allows it to compensate for
wide variations in transmitter data rate. The decoder
contains sophisticated error checking algorithms to
ensure only valid codes are accepted.
© 1997 Microchip Technology Inc.
DS40151C-page 1
1 page  
HCS512
3.0 DESCRIPTION OF FUNCTIONS
3.1 Parallel Interface
The HCS512 activates the S3, S2, S1 & S0 outputs
according to Table 3-1 when a new valid code is
received. The outputs will be activated for approxi-
mately 500 ms. If a repeated code is received during
this time, the output extends for approximately 500 ms.
TABLE 3-1: FUNCTION OUTPUT TABLE
Function
Code
S3
S2
S1
S0
0001
0
0
0
1
0010
0
0
1
0
0011
0
0
1
1
0100
0
1
0
0
0101
0
1
0
1
0110
0
1
1
0
0111
0
1
1
1
1000
1
0
0
0
1001
1
0
0
1
1010
1
0
1
0
1011
1
0
1
1
1100
1
1
0
0
1101
1
1
0
1
1110
1
1
1
0
1111
1
1
1
1
FIGURE 3-1: DATA OUTPUT FORMAT
START
S3
S2
S1
S0
3.2 Serial Interface
The decoder has a PWM/Synchronous interface con-
nection to microcontrollers with limited I/O. An output
data stream is generated when a valid transmission is
received. The data stream consists of one start bit, four
function bits, one bit for battery status, one bit to indi-
cate a repeated transmission, two status bits, and one
stop bit. (Table 3-1). The DATA and CLK lines are used
to send a synchronous event message.
A special status message is transmitted on the second
pass of learn. This allows the controlling microcontroller
to determine if the learn was successful (Result = 1)
and if a previous transmitter was overwritten (Overwrite
= 1). The status message is shown in Figure 3-2.
Table 3-2 show the values for TX1:0 and the number of
transmitters learned.
TABLE 3-2: STATUS BITS
TX1 TX0 Number of Transmitters
00
One
01
10
11
Two
Three
Four
VLOW REPEAT TX1
TX0 STOP
FIGURE 3-2: STATUS MESSAGE FORMAT
START
0
0
0
0
RESULT OVRWR TX1
TX0 STOP
A 1-wire PWM or 2-wire synchronous interface can be used.
In 1-wire mode, the data is transmitted as a PWM signal with a basic pulse width of 400 µs.
In 2-wire mode, synchronous mode PWM bits start on the rising edge of the clock, and the bits must be sampled on the
falling edge. The start and stop bits are ‘1’.
FIGURE 3-3: PWM TRANSMISSION FORMAT
600µs
CLK
DATA
Start
S3 S2 S1 S0 VLOW RPT Reserved Reserved Stop
1200µs
“1”
“0”
© 1997 Microchip Technology Inc.
DS40151C-page 5
5 Page 
HCS512
7.0 KEY GENERATION SCHEMES
The HCS512 decoder has two key generation schemes. Normal learning uses the transmitter’s serial number to derive
two input seeds which aµre used as inputs to the key generation algorithm. Secure learning uses the seed transmission
to derive the two input seeds. Two key generation algorithms are available to convert the inputs seeds to secret keys.
The appropriate scheme is selected in the configuration word.
FIGURE 7-1:
Serial
Number
Patched
Manufacturer’s
Key
Key Generation
Algorithms
-------------------
Decrypt
XOR
Encoder
Key
Seed
7.1 Normal Learning (Serial Number Derived)
The two input seeds are composed from the serial number in two ways, depending on the encoder type. The encoder
type is determined from the number of bits in the incoming transmission. SourceH is used to calculate the upper 32 bits
of the encoder key, and SourceL, for the lower 32 bits.
For 24-bit serial number encoders (56-bit transmissions):
SourceH = 65H + 24 bit Serial Number
SourceL = 2BH + 24 bit Serial Number
For 28-bit serial number encoders (66 / 67-bit transmissions):
SourceH = 6H + 28 bit Serial Number
SourceL = 2H + 28 bit Serial Number
7.2 Secure Learning (Seed Derived)
The two input seeds are composed from the seed value that is transmitted during secure learning. The lower 32 bits of
the seed transmission is used to compose the lower seed, and the upper 32 bits, for the upper seed. The upper 4 bits
(function code) are set to zero.
For 32-bit seed encoders:
SourceH = Serial Number Lower 28 bits with upper 4 bits always zero
SourceL = Seed 32 bits
For 48-bit seed encoders:
SourceH = Seed Upper 16 bits + Serial Number Upper 16 bits with upper 4 bits always zero
SourceL = Seed Lower 32 bits
For 64-bit seed encoders:
Note: 64-bit seeds are handled as 48-bit seeds
SourceH = Seed Upper 16 bits + Serial Number Upper 16 bits with upper 4 bits always zero
SourceL = Seed Lower 32 bits
© 1997 Microchip Technology Inc.
DS40151C-page 11
11 Page | ||
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