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PDF LC74986NWF Data sheet ( Hoja de datos )
| Número de pieza | LC74986NWF | |
| Descripción | LCD TV Scan Converter IC | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : ENN7713
SANYO Semiconductors
DATA SHEET
LC74986NWF CMOS IC
LC74986NWV LCD TV Scan Converter IC
Overview
The LC74986NWF and LC74986NWV are video signal processing ICs that perform resolution conversion, interlaced
to progressive scan (IP) conversion, and image quality improvement without requiring the use of external field (frame)
memory. These ICs can display a wide variety of video signals and formats on a flat panel display. These ICs also
provide image quality improvement and adjustment functions to create the optimal image quality for the flat panel
display used. They also include an OSD function that displays characters with the sizes optimal for the size of panel
used. A flat panel TV monitor with the necessary video signal processing circuits can be formed easily by combining
one of these ICs with a video decoder, A/D converters, a microcontroller, and an LCD panel.
Features
• Multi-source support
— NTSC, PAL, and DTV (480i and 480p) inputs
— Progressive scan inputs up to XGA (The LC74986NWV supports up to SVGA.)
— Supports both RGB and YCbCr (4:4:4 24 bits, 4:2:2 16 bits or 8 bits) inputs (built-in YCbCr to RGB converter).
• Resolution conversion
— Independent horizontal and vertical expansion and reduction in the horizontal direction
— Interlaced to progressive scan conversion
• Image quality correction
— Sharpness, color, tint, white/black stretch, brightness, contrast, white balance, black balance
— Built-in lookup table based gamma correction circuit (Common characteristics for each 8-bit RGB value can be
programmed.)
• Panel interface
— Single RGB 24-bit or 18-bit, or dual RGB 48-bit or 36-bit signal output (built-in dither processing)
— Horizontal sync signal, vertical sync signal, data enable signal, and pixel clock outputs
• Other features
— No external frame memory required (The input and output have the same frame period.)
— Built-in OSD function (510 characters, 8 colors, built-in 8-character font RAM)
— I2C bus interface (The OSD function can also be controlled over a 3-wire bus.)
— Low-power design
IC Specifications
• Supply voltage: I/O: 3.3V, core: 2.5V (LC74986NWF) or 1.8V (LC74986NWV) dual power supply system
• Maximum operating frequency: 85MHz (LC74986NWF), 40MHz (LC74986NWV)
• Package: 144-pin SQFP
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40804TN (OT) No.7713-1/15
1 page  
LC74986NWF, 74986NWV
• Control Signals
Signal type
Number of pins
Three-wire bus
signals
1
1
1
1
I2C bus signals
1
1
Symbol
AICS (VPBV)
AIDA
AICK
SDA
SCL
I2CSEL
Description
Three-wire bus chip select (port B
system vertical sync signal)
Data bus
Bus clock
Notes
• For OSD control (Normally, the I2C bus is used.)
Data bus
Bus clock
• Used for setting internal registers and for internal
status output.
• The slave address is 0111000 + (R/W)
• OSD control, gamma correction control
Slave switching
• Normally low. 0111000 + (R/W)
• Switches the IC to 0111001 + (R/W) when high.
• Other Signals
Signal type
Number of pins
Forcible mute
signal
1
Power down (low-
power mode) signal
2
1
Test signals
1
5
Symbol
Description
MUTE
Muting
PDOWN1
Low-power mode
PDOWN2 (VPBV) (Port B system vertical sync signal)
SCANEN
Test
SCANMOD
Test
TEST
Test
Notes
• The output can be forcibly muted from this pin.
Inverted logic
• Low-power mode used when the IC is not operating.
This pin is normally held at the high level.
• Used for test settings. This pin must be held at the
low level during normal operation.
• Used for test settings. This pin must be held at the
low level during normal operation.
• Used for test settings. This pin must be held at the
low level during normal operation.
No.7713-5/15
5 Page 
Input and Output Data Timing
• Input Data Timing 1
CLKI
Input data
tSU
LC74986NWF, 74986NWV
tHI
t LO
tHD
t CK
VDD/2
VDD/2
Items in parentheses refer to the LC74986NWV.
Pin Name
Parameter
Clock low level time
CLKI
Clock high level time
Clock period
VPA1 [7:0], VPA2 [7:0]
VPA3 [7:0], VSI, HSI,
DEVI, DEHI, CLKIEN
Input data setup time
Input data hold time
* : An input clock duty of 50% is recommended.
Symbol
tLO
tHI
tCK
tSU
tHD
min
5.5 (12.5)
5.5 (12.5)
11.0 (25.0)
3.0
3.0
max unit
— ns
— ns
— ns
— ns
— ns
• Input Data Timing 2
DCLKI
Input data
tSU
tHI
tLO
tHD
tCK
VDD/2
VDD/2
Items in parentheses refer to the LC74986NWV.
Pin Name
DCLKI
VPBEN, VPB1 [7:0],
VPB2 [7:0], VPB3 [7:0]
Parameter
Clock low level time
Clock high level time
Clock period
Input data setup time
Input data hold time
* : An input clock duty of 50% is recommended.
Symbol
tLO
tHI
tCK
tSU
tHD
min
5.5 (12.5)
5.5 (12.5)
11.0 (25.0)
3.0
3.0
max unit
— ns
— ns
— ns
— ns
— ns
No.7713-11/15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet LC74986NWF.PDF ] | |
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