IDT5P90005 Datasheet PDF - Integrated Device Technology
| Part Number | IDT5P90005 | |
| Description | SERIAL REAL-TIME CLOCK | |
| Manufacturers | Integrated Device Technology | |
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SERIAL REAL-TIME CLOCK
PRELIMINARY DATASHEET
IDT5P90005
Description
The IDT5P90005 is a serial real-time clock (RTC) device
that consumes ultra-low power and provides a full
binary-coded decimal (BCD) clock/calendar. The
clock/calendar provides seconds, minutes, hours, day,
date, month, and year information. The clock operates in
either the 24-hour or 12-hour format with AM/PM indicator.
The end of the month date is automatically adjusted for
months with fewer than 31 days, including corrections for
leap year. Access to the clock/calendar registers is
provided by an I2C interface capable of operating in fast I2C
mode. Built-in Power-sense circuitry detects power failures
and automatically switches to the backup supply,
maintaining time and date operation.
Features
• Packaged in 8-pin SOIC
• Counters for seconds, minutes, hours, days, date,
months, years, and century
• 32 kHz crystal oscillator integrating load capacitance
(12.5 pF) providing exceptional oscillator stability and
high crystal series resistance operation
• Serial interface supports I2C bus (100 or 400 kHz
protocol)
• Ultra low battery supply current of 0.8 µA (typ at 3 V)
• 2.0 to 5.5 V clock operating voltage
• Automatic switch over and deselect circuitry
• Automatic leap year compensation
• Operating temperature of -40 to +85°C
Block Diagram
OSCI
OSCO
VCC
GND
VBAT
SCL
SDA
32.768 kHz
Oscillator and
Divider
1 Hz
MUX/
Buffer
Power
Control
Control
Logic
Clock, Calendar
Counter
I2C
Interface
1 Byte 7 Bytes
Control Buffer
FT/OUT
IDT™ SERIAL REAL-TIME CLOCK
1
IDT5P90005 REV E 031209
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IDT5P90005
SERIAL REAL-TIME CLOCK
Data Transfer on I2C Serial Bus
RTC
Depending upon the state of the R/W bit, two types of data
transfer are possible:
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.
Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is transmitted by
the master. The slave then returns an acknowledge bit. This
is followed by the slave transmitting a number of data bytes.
The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received
byte, a “not acknowledge” is returned. The master device
generates all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition
or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the bus is not released. Data is transferred with the
most significant bit (MSB) first.
The IDT5P90005 can operate in the following two modes:
1) Slave Receiver Mode (Write Mode): Serial data and
clock are received through SDA and SCL. After each byte is
received an acknowledge bit is transmitted. START and
STOP conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction
bit (see the “Data Write–Slave Receiver Mode” figure). The
slave address byte is the first byte received after the START
condition is generated by the master. The slave address
byte contains the 7-bit IDT5P90005 address, which is
1101000, followed by the direction bit (R/W), which is 0 for
a write. After receiving and decoding the slave address byte
the slave outputs an acknowledge on the SDA line. After the
IDT5P90005 acknowledges the slave address + write bit,
the master transmits a register address to the IDT5P90005.
This sets the register pointer on the IDT5P90005, with the
IDT5P90005 acknowledging the transfer. The master may
then transmit zero or more bytes of data, with the
IDT5P90005 acknowledging each byte received. The
address pointer increments after each data byte is
transferred. The master generates a STOP condition to
terminate the data write.
2) Slave Transmitter Mode (Read Mode): The first byte is
received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the
transfer direction is reversed. Serial data is transmitted on
SDA by the IDT5P90005 while the serial clock is input on
SCL. START and STOP conditions are recognized as the
beginning and end of a serial transfer (see the “Data
Read–Slave Transmitter Mode” figure). The slave address
byte is the first byte received after the START condition is
generated by the master. The slave address byte contains
the 7-bit IDT5P90005 address, which is 1101000, followed
by the direction bit (R/W), which is 1 for a read. After
receiving and decoding the slave address byte the slave
outputs an acknowledge on the SDA line. The IDT5P90005
IDT™ SERIAL REAL-TIME CLOCK
5
IDT5P90005 REV E 031209
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IDT5P90005 electronic component. |
| Information | Total 16 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IDT5P90005.PDF Datasheet ] | |
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| Part Number | Description | MFRS |
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