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Integrated Device Technology - LOW POWER CLOCK GENERATOR

Numéro de référence IDT5P49EE802
Description LOW POWER CLOCK GENERATOR
Fabricant Integrated Device Technology 
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IDT5P49EE802 fiche technique
PRELIMINARY DATASHEET
VERSACLOCK® LOW POWER CLOCK GENERATOR
IDT5P49EE802
Description
The IDT5P49EE802 is a programmable clock generator
intended for low power, battery operated consumer
applications. There are four internal PLLs, each individually
programmable, allowing for up to eight differrent output
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from either
a TCXO or fundamental mode crystal. An additional 32kHz
crystal oscillator is available to provide a real time clock or
non-critical performance MHz processor clock.
The IDT5P49EE802 can be programmed through the use
of the I2C interfaces. The programming interface enables
the device to be programmed when it is in normal operation
or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore
the configuration of the device without having to reprogram
it on power-up.
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation is
supported on one of the PLLs.
Spread spectrum generation is supported on one of the
PLLs. The device is specifically designed to work with
display applications to ensure that the spread profile
remains consistent for each HSYNC in order to reduce
ROW noise. It also may operate in standard spread
sepctrum mode.
There are total six 8-bit output dividers. Outputs are
LVCMOS. The outputs are connected to the PLLs via the
switch matrix. The switch matrix allows the user to route the
PLL outputs to any output bank. This feature can be used to
simplify and optimize the board layout. In addition, each
output's slew rate and enable/disable function can be
programmed.
Target Applications
Smart Mobile Handset
Personal Navigation Device (PND)
Camcorder
DSC
Portable Game Console
Personal Media Player
Features
Four internal PLLs
Internal non-volatile EEPROM
Internal I2C EEPROM master interface
FAST (400kHz) mode I2C serial interfaces
Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
– RTC Crystal: 32.768 kHz
Output Frequency Ranges: kHz to 120 MHz
Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
8-bit output-divider blocks
One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock
with no visible artifacts
I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
3 independent adjustable VDDO groups.
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Individual output enable/disable
Power-down/Sleep mode
– 10A max in power down mode
– 32kHz clock output active sleep mode
– 100A max in sleep mode
1.8V VDD Core Voltage
Available in 28 pin 4x4mm QFN packages
-40 to +85 C Industrial Temp operation
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
1
IDT5P49EE802 REV C 061810

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