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PDF IDT5P49V5901 Data sheet ( Hoja de datos )
| Número de pieza | IDT5P49V5901 | |
| Descripción | Programmable Clock Generator | |
| Fabricantes | Integrated Device Technology | |
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Programmable Clock Generator
IDT5P49V5901
PRELIMINARY DATASHEET
Description
Features
The IDT5P49V5901 is a programmable clock generator
intended for high performance consumer, networking,
industrial, computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock.
The reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
XOUT
XIN/REF
VDDA
CLKSEL
24 23 22 21 20 19
1 18
2 17
3 16
EPAD
4 15
5 14
6 13
7 8 9 10 11 12
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
24-pin VFQFPN
• Generates up to four independent output frequencies
• High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
• Four fractional output dividers (FODs)
• Independent Spread Spectrum capability on each output
pair
• Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
• I2C serial programming interface
• One reference LVCMOS output clock
• Four universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
• I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
• Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 5MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 5MHz to 350MHz
– Crystal frequency range: 8MHz to 40MHz
• Output frequency ranges:
– LVCMOS Clock Outputs – 5MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
5MHz to 350MHz
• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
• Redundant clock inputs with manual switchover
• Programmable loop bandwidth
• Programmable slew rate control
• Programmable crystal load capacitance
• Individual output enable/disable
• Power-down mode
• 1.8V, 2.5V or 3.3V core VDDD, VDDA
• Available in 24-pin VFQFPN 4mm x 4mm package
• -40° to +85°C industrial temperature operation
IDT5P49V5901 REVISION B 06/04/14
1
©2014 Integrated Device Technology, Inc.
1 page  
IDT5P49V5901 PRELIMINARY DATASHEET
Reference Clock Input Pins and
Selection
The IDT5P49V5901 supports up to two clock inputs. One of
the clock inputs (XIN/ REF) can be driven by either an external
crystal or a reference clock. The second clock input (CLKIN,
CLKINB) can only be driven from an external reference clock.
The CLKSEL pin selects the input clock between either
XTAL/REF or (CLKIN, CLKINB).
Either clock input can be set as the primary clock. The primary
clock designation is to establish which is the main reference
clock to the PLL. The non-primary clock is designated as the
secondary clock in case the primary clock goes absent and a
backup is needed. The PRIMSRC bit determines which clock
input will be selected as primary clock. When PRIMSRC bit is
“0”, XIN/REF is selected as the primary clock, and when “1”,
(CLKIN, CLKINB) as the primary clock.
The two external reference clocks can be manually selected
using the CLKSEL pin. The SM bits must be set to “0x” for
manual switchover which is detailed in Manual Switchover
Mode section.
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
When a crystal is connected across the XIN/REF and XOUT
pins it is important to set the internal tuning capacitor values
correctly to achieve the highest clock frequency accuracy.
There are two equal valued tuning capacitors, one for XIN and
one for XOUT and each capacitor provides a parallel path for
its associated pin to the internal ground of the device. The
values of these capacitors are composed of a fixed capacity
plus a variable capacity set with the XTAL[5:0] register
through the I2C interface. Adjustment of the crystal tuning
capacitors through firmware allows for maximum flexibility to
accommodate crystals from various manufacturers. The
range of tuning capacitor values available are in accordance
with the following table.
XTAL[5:0] Tuning Capacitor Characteristics
Parameter
XTAL
Bits Step (pF) Min (pF)
6 0.5
0
Max (pF)
16
The AC voltages on the XIN and XOUT pins are out of phase,
which allows the two XTAL[5:0] tuning capacitors to be
translated into a single equivalent parallel load capacitor
across XIN and XOUT by dividing the tuning capacity by two.
Adding the fixed parallel capacity and the effective parallel
tuning capacity set by XTAL results in the total parallel tuning
capacity provided by the VersaClock.
XTAL load cap = 4.5pF + (XTAL[5:0]/2) (Eq. 1)
Equation 1 and the table of XTAL[5:0] tuning capacitor
characteristics show that the parallel tuning capacitance can
be set between 4.5pF to 12.5pF with a resolution of 0.25 pF.
Consider two examples.
For a crystal CL= 8pF, where CL is the parallel capacity
specified by the crystal vendor that sets the crystal frequency
to the nominal value. Under the assumptions that the stray
capacity between the crystal leads on the circuit board is zero
and that no external tuning caps are placed on the crystal
leads, then the internal parallel tuning capacity is equal to the
load capacity presented to the crystal by the VersaClock.
Equation 1 allows for the direct calculation that XTAL[5:0] = 14
(dec).
In the case of a CL = 18pF crystal, the maximum internal
parallel tuning cap of 12.5pF will be insufficient. Two external
tuning capacitors must be added to the circuit board, one on
each of XIN and XOUT. For maximum turning range, set the
value of the two external tuning caps so that XTAL[5:0] is set
in the middle of its range, 8pF/2 = 4pF and XTAL[5:0] = 32
(dec). Using Equation 1, the internal tuning capacitor is set for
4.5pF + 4pF = 8.5pF. The remaining tuning capacity is 18pF -
8.5pF = 9.5pF. Each external tuning capacitor is then 2*9.5pF
= 19pF.
The internal load capacitors are true parallel-plate capacitors
for ultra-linear performance. Parallel-plate capacitors were
chosen to reduce the frequency shift that occurs when
non-linear load capacitance interacts with load, bias, supply,
and temperature changes. External non-linear crystal load
capacitors should not be used for applications that are
sensitive to absolute frequency requirements.
Manual Switchover Mode
When SM[1:0] is “0x”, the redundant inputs are in manual
switchover mode. In this mode, CLKSEL pin is used to switch
between the primary and secondary clock sources. The
primary and secondary clock source setting is determined by
the PRIMSRC bit. During the switchover, no glitches will occur
at the output of the device, although there may be frequency
and phase drift, depending on the exact phase and frequency
relationship between the primary and secondary clocks.
REVISION B 06/04/14
5 PROGRAMMABLE CLOCK GENERATOR
5 Page 
IDT5P49V5901 PRELIMINARY DATASHEET
Table 10:Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down
Resistance (TA = +25 °C)
Symbol
CIN
Pull-down
Resistor
ROUT
XIN/REF,
XOUT
Parameter
Input Capacitance (CLKIN, CLKINB, CLKSEL, SD/OE, SEL1/SDA,
SEL0/SCL)
CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL, CLKIN, CLKINB,
OUT0_SEL_I2CB
LVCMOS Output Driver Impedance (VDDO = 1.8V, 2.5V, 3.3V)
Programmable input capacitance at XIN/REF and XOUT
Min Typ Max Unit
3 7 pF
100 k
17
0 8 pF
Table 11:Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance (CL)
Maximum Crystal Drive Level
Test Conditions
Min Typ Max
Fundamental
8 40
10 100
27
8 12 18
100
Units
MHz
pF
pF
µW
Table 12:DC Electrical Characteristics
Symbol
Parameter
Iddcore3 Core Supply Current
Test Conditions
100 MHz on all outputs,
25 MHz REFCLK
Iddox
Output Buffer Supply Current
LVPECL, 350 MHz, 3.3V VDDOX
LVPECL, 350 MHz, 2.5V VDDOX
LVDS, 350 MHz, 3.3V VDDOX
LVDS, 350 MHz, 2.5V VDDOX
Iddpd Core Power Down Current
LVDS, 350 MHz, 1.8V VDDOX
HCSL, 250 MHz, 3.3V VDDOX, 2 pF load
HCSL, 250 MHz, 2.5V VDDOX, 2 pF load
LVCMOS, 50 MHz, 3.3V VDDOX, 1,2
LVCMOS, 50 MHz, 2.5V VDDOX, 1,2
LVCMOS, 50 MHz, 1.8V VDDOX, 1,2
LVCMOS, 200 MHz, 3.3V VDDOX, 1,2
LVCMOS, 200 MHz, 2.5V VDDOX, 1,2
LVCMOS, 200 MHz, 1.8V VDDOX, 1,2
SD asserted, I2C Programming
1.Single CMOS driver active.
2.Measured into a 5” 50 Ohm trace with 2 pF load.
3. Iddcore = IddA + IddD, no loads.
Min Typ
30
61
52
18
17
16
29
28
16
14
12
36
27
16
5
Max
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
REVISION B 06/04/14
11 PROGRAMMABLE CLOCK GENERATOR
11 Page | ||
| Páginas | Total 35 Páginas | |
| PDF Descargar | [ Datasheet IDT5P49V5901.PDF ] | |
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