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PDF HCS04D Data sheet ( Hoja de datos )

Número de pieza HCS04D
Descripción Radiation Hardened Hex Inverter
Fabricantes Intersil Corporation　
Logotipo Intersil Corporation Logotipo



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HCS04MS
August 1995
Radiation Hardened
Hex Inverter
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10-9 Errors/Gate Day
(Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCS04MS is a Radiation Hardened Hex Inverter. A
logic level on any input forces the output to the opposite logic
state.
The HCS04MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS04MS is supplied in a 14 lead Ceramic flatpack (K suffix)
or a SBDIP Package (D suffix).
A1
Y1
A2
Y2
A3
Y3
GND
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
A1 1
Y1 2
A2 3
Y2 4
A3 5
Y3 6
GND 7
14 VCC
13 A6
12 Y6
11 A5
10 Y5
9 A4
8 Y4
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
TRUTH TABLE
INPUTS
OUTPUTS
VCC
A6
Y6
A5
Y5
A4
Y4
Ordering Information
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCS04DMSR -55oC to +125oC Intersil Class 14 Lead SBDIP
S Equivalent
HCS04KMSR -55oC to +125oC Intersil Class 14 Lead Ceramic
S Equivalent Flatpack
HCS04D/
Sample
+25oC
Sample
14 Lead SBDIP
HCS04K/
Sample
+25oC
Sample
14 Lead Ceramic
Flatpack
HCS04HMSR
+25oC
Die
Die
An Yn
LH
HL
NOTE: L = Logic Level Low,
H = Logic level High
Functional Diagram
An
(1, 3, 5, 9, 11, 13)
Yn
(2, 4, 6, 8, 10, 12)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
25
Spec Number 518745
File Number 3046.1

1 page




HCS04D pdf
Specifications HCS04MS
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE
GROUPS
METHOD
TEST
PRE RAD
POST RAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
READ AND RECORD
PRE RAD
POST RAD
1, 9 Table 4 (Note 1)
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V
50kHz
25kHz
STATIC BURN-IN I TEST CONDITIONS (Note 1)
2, 4, 6, 8, 10, 12
1, 3, 5, 7, 9, 11, 13
-
14 - -
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
2, 4, 6, 8, 10, 12
7
-
1, 3, 5, 9, 11, 13, 14
-
-
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)
-
7
2, 4, 6, 8, 10, 12
14
1, 3, 5, 9, 11, 13
-
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in.
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
2, 4, 6, 8, 10, 12
7
1, 3, 5, 9, 11, 13, 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 518745
29

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