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PDF LTC6948 Data sheet ( Hoja de datos )
| Número de pieza | LTC6948 | |
| Descripción | Ultralow Noise 0.37GHz to 6.39GHz Fractional-N Synthesizer | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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1. LTC6948  Hay una vista previa y un enlace de descarga de LTC6948 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Features
LTC6948
Ultralow Noise 0.37GHz to
6.39GHz Fractional-N Synthesizer
with Integrated VCO
Description
n Low Noise Fractional-N PLL with Integrated VCO
n No ∆-∑ Modulator Spurs
n 18-Bit Fractional Denominator
n –226 dBc/Hz Normalized In-Band Phase Noise Floor
n –274 dBc/Hz Normalized In-Band 1/f Noise
n –157 dBc/Hz Wideband Output Phase Noise Floor
n Excellent Integer Boundary Spurious Performance
n Output Divider (1 to 6, 50% Duty Cycle)
n Output Buffer Muting
n Reference Input Frequency Up to 425MHz
n Fast Frequency Switching
n FracNWizard™ Software Design Tool Support
Applications
n Wireless Basestations (LTE, WiMAX, W-CDMA, PCS)
n Microwave Data Links
n Military and Secure Radio
n Test and Measurement
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
FracNWizard is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
The LTC®6948 is a high performance, low noise, 6.39GHz
phase-locked loop (PLL) with a fully integrated VCO,
including a reference divider, phase-frequency detector
(PFD), ultralow noise charge pump, fractional feedback
divider, and VCO output divider.
The fractional divider uses an advanced, 4th order Δ∑
modulator which provides exceptionally low spurious
levels. This allows wide loop bandwidths, producing ex-
tremely low integrated phase noise values.
The programmable VCO output divider, with a range of 1
through 6, extends the output frequency range.
Output Frequency Options
LTC6948-1 LTC6948-2 LTC6948-3 LTC6948-4
O_DIV = 1 2.240 to 3.740 3.080 to 4.910 3.840 to 5.790 4.200 to 6.390
O_DIV = 2 1.120 to 1.870 1.540 to 2.455 1.920 to 2.895 2.100 to 3.195
O_DIV = 3 0.747 to 1.247 1.027 to 1.637 1.280 to 1.930 1.400 to 2.130
O_DIV = 4 0.560 to 0.935 0.770 to 1.228 0.960 to 1.448 1.050 to 1.598
O_DIV = 5 0.448 to 0.748 0.616 to 0.982 0.768 to 1.158 0.840 to 1.278
O_DIV = 6 0.373 to 0.623 0.513 to 0.818 0.640 to 0.965 0.700 to 1.065
Typical Application
6.3GHz Wideband Receiver
1.6nF
76.8Ω 10µH
0.1µF 3.3V
5V
15Ω
1µF 2.4nF
76.8Ω
0.1µF
UNUSED OUTPUT
AVAILABLE FOR
OTHER USE
50Ω
1µF
100MHz
51.1Ω
SPI BUS
3.3V
0.1µF
3.3V
3.3V
0.1µF
1µF 0.01µF
56nF
0.01µF
1µF
REF+
STAT
CS
SCLK
SDI
SDO
LDO
VD+
LTC6948-4
BVCO
GND
CMA
CMB
CMC
GND
TB
TUNE
2.2µF
68nH
68nH 100pF
3.3V
0.01µF
R = 2, fPFD = 50MHz
1µF
N = 84 TO 127.8
LBW = 186kHz
O=1
100pF
fLO = 4200MHz TO 6390MHz IN 190.7Hz STEPS
RF INPUT SIGNAL
LO IF
RF
IF OUTPUT
6948 TA01a
LTC6948-4 Phase Noise,
fRF = 6236MHz
–90
–100
–110
–120
–130
RMS NOISE = 0.412°
–140 RMS JITTER = 183fs
fPFD = 50MHz
–150
LOOP BW = 186kHz
INTN = 0
–160 CPLE = 1
100 1k 10k 100k
1M
OFFSET FREQUENCY (Hz)
10M 40M
6946 TA01b
For more information www.linear.com/LTC6948
6948f
1
1 page  
LTC6948
E lectrical Characteristics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are
specified (Note 2). All voltages are with respect to GND.
at
TA
=
25°C.
VREF+
=
VD+
=
VRF+
=
3.3V,
VCP+
=
VVCO+
=
5V
unless
otherwise
SYMBOL
PARAMETER
CONDITIONS
ICC(3.3V)
Sum VREF+, VRF+ Supply Currents
RF Muted, OD[2:0] = 1
RF Enabled, RFO[1:0] = 0, OD[2:0] = 1
RF Enabled, RFO[1:0] = 3, OD[2:0] = 1
RF Enabled, RFO[1:0] = 3, OD[2:0] = 2
RF Enabled, RFO[1:0] = 3, OD[2:0] = 3
RF Enabled, RFO[1:0] = 3, OD[2:0] = 4 to 6
PDALL = 1
Phase Noise and Spurious
LVCO
VCO
fRF =
P3h.0aGseHzN,oOisDe[2(L:0T]C=6914(8N-o1t,efV6C)O)
=
3.0GHz,
10kHz Offset
1MHz Offset
40MHz Offset
VCO Phase Noise (LTC6948-2, fVCO = 4.0GHz, 10kHz Offset
fRF = 4.0GHz, OD[2:0] = 1 (Note 6))
1MHz Offset
40MHz Offset
VCO Phase Noise (LTC6948-3, fVCO = 5.0GHz, 10kHz Offset
fRF = 5.0GHz, OD[2:0] = 1 (Note 6))
1MHz Offset
40MHz Offset
VCO Phase Noise (LTC6948-4, fVCO = 6.0GHz, 10kHz Offset
fRF = 6.0GHz, OD[2:0] = 1 (Note 6))
1MHz Offset
40MHz Offset
VCO Phase Noise (LTC6948-3, fVCO = 5.0GHz, 10kHz Offset
fRF = 2.50GHz, OD[2 :0] = 2 (Note 6))
1MHz Offset
40MHz Offset
VCO Phase Noise (LTC6948-3, fVCO = 5.0GHz, 10kHz Offset
fRF = 1.667GHz, OD[2 :0] = 3 (Note 6))
1MHz Offset
40MHz Offset
VCO Phase Noise (LTC6948-3, fVCO = 5.0GHz, 10kHz Offset
fRF = 1.25GHz, OD[2 :0] = 4 (Note 6))
1MHz Offset
40MHz Offset
VCO Phase Noise (LTC6948-3, fVCO = 5.0GHz, 10kHz Offset
fRF = 1.00GHz, OD[2 :0] = 5 (Note 6))
1MHz Offset
40MHz Offset
l
l
l
l
l
l
l
MIN
TYP
70.4
81.1
91.3
109.2
114.8
119.6
53
–80
–130
–157
–77
–127
–156
–75
–126
–155
–73
–123
–154
–81
–132
–155
–84
–135
–156
–87
–138
–156
–89
–140
–157
MAX UNITS
80 mA
95 mA
105 mA
125 mA
135 mA
140 mA
250 µA
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
VCO
fRF =
P0h.8a3s3eGNHozis, eO(DL[T2C :609] 4=86-3(,NfoVCteO6=))5.0GHz,
10kHz Offset
1MHz Offset
40MHz Offset
–90 dBc/Hz
–141 dBc/Hz
–158 dBc/Hz
LNORM(INT)
Integer Normalized In-Band Phase Noise
Floor
INTN = 1, ICP = 5.6mA (Notes 7, 8, 10)
–226 dBc/Hz
LNORM(FRAC)
L1/f
Fractional Normalized In-Band Phase Noise
Floor
Normalized In-Band 1/f Phase Noise
In-Band Phase Noise Floor
Integrated Phase Noise from 100Hz to
40MHz
Spurious
INTN =
(Notes
0,
7,
CPLE
8, 10)
=
1,
ICP
=
5.6mA
ICP = 11.2mA (Notes 7, 11)
Fractional Mode, CPLE = 1
(Notes 7, 9, 10, 12)
Fractional Mode, CPLE = 1 (Notes 9, 12)
Fractional Mode, fOFFSET = fPFD, PLL locked
(Notes 8, 13, 14)
–225 dBc/Hz
–274 dBc/Hz
–113 dBc/Hz
0.14 °RMS
–98 dBc
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6948I is guaranteed to meet specified performance limits
over the full operating junction temperature range of –40°C to 105°C.
For more information www.linear.com/LTC6948
6948f
5
5 Page 
LTC6948
Pin Functions
REF+, REF– (Pins 1, 28): Reference Input Signals. This
differential input is buffered with a low noise amplifier,
which feeds the reference divider. They are self-biased and
must be AC-coupled with 1µF capacitors. If used single-
eb1nyµdpFeacdsaspwRaictEhiFto–VrRt.oEIfFG+uNs≤eD2d.w7siiVtnhPg-alPe,-4eb7nypdpFeacdsaswpRaitEchiFtV–oRrt.EoF+G>ND2.7wVitPh-Pa,
STAT (Pin 2): Status Output. This signal is a configurable
logical OR combination of the UNLOK, LOK, ALCHI, ALCLO,
THI, and TLO status bits, programmable via the STATUS
register. See the Operation section for more details.
CS (Pin 3): Serial Port Chip Select. This CMOS input initi-
ates a serial port communication burst when driven low,
ending the burst when driven back high. See the Operation
section for more details.
SCLK (Pin 4): Serial Port Clock. This CMOS input clocks
serial port input data on its rising edge. See the Operation
section for more details.
SDI (Pin 5): Serial Port Data Input. The serial port uses
this CMOS input for data. See the Operation section for
more details.
SDO (Pin 6): Serial Port Data Output. This CMOS three-
state output presents data from the serial port during a
read communication burst. Optionally attach a resistor of
>200k to GND to prevent a floating output. See the Ap-
plications Information section for more details.
LDO (Pin 7): Δ∑ Modulator LDO Bypass Pin. This pin
should be bypassed directly to the ground plane using a
low ESR (<0.8Ω) 0.1µF ceramic capacitor as close to the
pin as possible.
VD+ (Pin 8): 3.15V to 3.45V Positive Supply Pin for Serial
Port and Δ∑ Modulator Circuitry. This pin should be by-
passed directly to the ground plane using a 0.1µF ceramic
capacitor as close to the pin as possible.
MUTE (Pin 9): RF Mute. The CMOS active-low input mutes
the RF± differential outputs while maintaining internal bias
levels for quick response to deassertion.
GND (Pins 10, 17, 21, Exposed Pad Pin 29): Negative
Power Supply (Ground). These pins should be tied directly
to the ground plane with multiple vias for each pin. The
package exposed pad must be soldered directly to the PCB
land. The PCB land pattern should have multiple thermal
vias to the ground plane for both low ground inductance
and also low thermal resistance.
RF–, RF+ (Pins 11, 12): RF Output Signals. The VCO
output divider is buffered and presented differentially on
these pins. The outputs are open-collector, with 136Ω
(typical) pull-up resistors tied to VRF+ to aid impedance
matching. If used single-ended, the unused output should
be terminated to 50Ω. See the Applications Information
section for more details on impedance matching.
VRF+ (Pin 13): 3.15V to 3.45V Positive Supply Pin for
RF circuitry. This pin should be bypassed directly to the
ground plane using a 0.01µF ceramic capacitor as close
to the pin as possible.
BB (Pin 14): RF Reference Bypass. This output has a 2.5k
resistance and must be bypassed with a 1µF ceramic ca-
pacitor to GND. Do not couple this pin to any other signal.
TUNE (Pin 15): VCO Tuning Input. This frequency control
pin is normally connected to the external loop filter. See
the Applications Information section for more details.
For more information www.linear.com/LTC6948
6948f
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC6948.PDF ] | |
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