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PDF EN5396QI Data sheet ( Hoja de datos )
| Número de pieza | EN5396QI | |
| Descripción | 9A PowerSoC Synchronous DC-DC Buck Converter | |
| Fabricantes | Altera | |
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Enpirion® Power Datasheet
EN5396QI 9A PowerSoC
Synchronous DC-DC Buck Converter
with Integrated Inductor
Description
The EN5396QI is a Power Supply on a Chip
(PwrSoC) DC-DC converter. It is specifically
designed to meet the precise voltage and fast
transient requirements of present and future
high-performance, low-power processor, DSP,
FPGA, ASIC, memory boards, and system level
applications in a distributed power architecture.
Advanced circuit techniques, ultra high switching
frequency, and innovative, high-density,
integrated circuit and proprietary inductor
technology deliver high-quality, ultra compact,
non-isolated DC-DC conversion. Operating this
converter requires as few as five external
components that include small value input and
output ceramic capacitors and a soft-start
capacitor.
The Altera Enpirion solution significantly helps in
system design and productivity by offering greatly
simplified board design, layout and
manufacturing requirements. In addition, a
reduction in the number of vendors required for
the complete power solution helps to enable an
overall system cost savings.
Applications
• Point of load regulation for low-power
processors, network processors, DSPs,
FPGAs, and ASICs
• Notebook computers, servers, workstations
• Broadband, networking, LAN/WAN, optical
• Low voltage, distributed power architectures
with 2.5V, 3.3V or 5V rails
• DSL, STB, DVR, DTV, Industrial PC
• Noise sensitive applications
Features
10mm
12mm
• Integrated Inductor Technology: Integrated
Inductor, MOSFETS, Controller in a 10 x 12 x
1.85mm package
• Low External Part Count.
• Up to 30W continuous output power.
• Low output impedance optimized for ≤ 90 nm
• Master/slave configuration for paralleling.
• 5MHz operating frequency.
• High efficiency, up to 93%.
• Wide input voltage range of 2.375V to 5.5V.
• External resistor divider output voltage select.
• Output Enable pin and Power OK signal.
• Programmable soft-start time.
• Adjustable over-current protection.
• Thermal shutdown, short circuit, over-voltage
and under-voltage protection.
• RoHS compliant, MSL level 3, 260C reflow.
Typical Application Circuit
VIN
2 x 47µF
1Ω PVIN VOUT
AVIN
ENABLE
XOV
PGND XFB
SS
15nF
VOUT
2 x 47µF
AGND PGND
Ordering Information
Part Number Temp Rating (°C)
Package
EN5396QI
-40 to +85
58-pin QFN T&R
EVB-EN5396QI
QFN Evaluation Board
Figure 1. Simple Layout.
02393
October 11, 2013
www.altera.com/enpirion
Rev E
1 page  
EN5396QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond
recommended operating conditions is not implied. Stress beyond absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER
Input Supply Voltage
Voltages on: ENABLE, VSENSE, XFB, XOV, M/S
Voltages on: EAIN, EAOUT, COMP
Voltages on: SS, PWM
Voltages on: POK
Storage Temperature Range
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
SYMBOL
VIN
TSTG
MIN
-0.5
-0.5
-0.5
-0.5
-0.5
-65
2000
MAX
7.0
VIN
2.5
3.0
VIN + 0.3
150
260
UNITS
V
V
°C
°C
V
Recommended Operating Conditions
PARAMETER
SYMBOL
Input Voltage Range
VIN
Output Voltage Range (NOTE: 1)
VOUT
Output Current (NOTE 2)
IOUT
Operating Ambient Temperature
TA
Operating Junction Temperature
TJ
Note 1: VDROPOUT = ILOAD x Dropout Resistance
Note 2: Reference figures 5 and 6 for the Output Current Derating Curves.
MIN
2.375
0.75
0
-40
-40
MAX
5.5
VIN - VDROPOUT
9
+85
+125
UNITS
V
V
A
°C
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
Thermal Resistance: Junction to Ambient (0 LFM) (Note 3)
Thermal Resistance: Junction to Case (0 LFM)
Thermal Overload Trip Point
Thermal Overload Trip Point Hysteresis
θJA
θJC
TJ-TP
18
1.5
+150
20
Note 3: Based on four layer board and proper thermal design in line with JEDEC EIJ/JESD 51 standards
UNITS
°C/W
°C/W
°C
°C
Electrical Characteristics
NOTE: VIN=5.5V over operating temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
VOUT Initial Accuracy
Overall VOUT Accuracy
(Line, Load, and
Temperature combined)
Transient Response Peak
Deviation
Under Voltage Lock out
threshold
Switching Frequency
02393
SYMBOL TEST CONDITIONS
∆VOUT_INIT
∆VOUT_ALL
∆VOUT
VUVLO
FSWITCH
TA = 25C, 2.375V ≤ VIN ≤ 5.5V
ILOAD = 1A; TA = 25°C
2.4V ≤ VIN ≤ 5.5V
-40°C ≤ TA ≤ +85°C
0A ≤ ILOAD ≤ 9A
(IOUT = 0% to 100% or 100% to
0% or rated load)
VIN = 5V, 1.2V ≤ VOUT ≤ 3.3V
COUT = 2 x 47 μF
VIN Increasing
VIN Decreasing
5
October 11, 2013
MIN
-2
-3%
TYP
MAX UNITS
2%
+3%
3%
2.2
2.1
V
5 MHz
www.altera.com/enpirion
Rev E
5 Page 
event of an over-voltage condition the POK
signal will go low and will remain in this condition
until the output voltage has dropped to 95% of
the programmed output voltage before returning
to the high state.
The internal POK FET is designed to tolerate up
to 4mA. The pull-up resistor value should be
chosen to limit the current from exceeding this
value when POK is logic low.
Over-Current Protection
When an over current condition occurs, VOUT is
pulled low. This condition is maintained for a
period of 1.2 ms and then a normal soft start
cycle is initiated. If the over current condition still
persists, this cycle will repeat.
EN5396QI
Compensation
The EN5396 is internally compensated through
the use of a type 3 compensation network and is
optimized for use with about 50μF of output
capacitance and will provide excellent loop
bandwidth and transient performance for most
applications. (See the section on Capacitor
Selection for details on recommended capacitor
types.) Voltage mode operation provides high
noise immunity at light load.
In some cases modifications to the compensation
may be required. The EN5396QI provides access
to the internal compensation network to allow for
customization. For more information, contact
Altera Power Applications support.
The OCP trip point is nominally set to 150% of
maximum rated load. It is possible to increase
the OCP trip point to 200% of the maximum rated
load by connecting a 5kΩ resistor between the
ROCP pin (pin 38) and AGND (pin 39). This
option is intended for startup into capacitive
loads such as certain FPGAs and ASICs.
Over-Voltage Protection
When the output voltage exceeds 120% of the
programmed output voltage, the PWM operation
stops, the lower N-MOSFET is turned on and the
POK signal goes low. When the output voltage
drops below 95% of the programmed output
voltage, normal PWM operation resumes and
POK returns to its high state.
Thermal Overload Protection
Thermal shutdown will disable operation once
the Junction temperature exceeds approximately
150ºC. Once the junction temperature drops by
approx 20ºC, the converter will re-start with a
normal soft-start.
Input Under-voltage Lock-out
Circuitry is provided to ensure that when the
input voltage is below the specified voltage
range, the converter will not start-up. Circuits for
hysteresis, input de-glitch and output leading
edge blanking are included to ensure high noise
immunity and prevent false tripping.
Parallel Device Operation
In order to power a load that is higher than the
rated 9A of the EN5396, from 2 to 4 devices can
be placed in parallel for providing a single load
with up to 24A of output current.
Paralleling more than 1 device is accomplished
by selecting a master device and tying that M/S
pin to AGND. All slave devices should have their
M/S pin tied to AVIN. The PWM pin from the
master device is connected to all slave device
PWM pins. The PWM signal is a 5 MHz drive
signal and must be routed appropriately. (See
Figure 4.)
1. All master and slave devices should have
identical placement and values of input,
output and soft-start capacitors.
2. All master and slave devices should have
their ENABLE pins tied together and
should be operated simultaneously with a
fast rising edge of 10 uSec or less, to
ensure that devices start up at the same
time. Startup imbalance could lead to
OCP condition on first device to startup.
3. The maximum board trace resistance
between any 2 devices VOUT pins should
be less than 10mΩ.
4. The maximum difference of PVIN between
any 2 devices should be less than 50mV.
02393
11
October 11, 2013
www.altera.com/enpirion
Rev E
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet EN5396QI.PDF ] | |
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