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HCPL-270L060 fiches techniques PDF

ETC - Low Input Current High Gain LVTTL/LVCMOS Compatible 3.3 V Optocouplers

Numéro de référence HCPL-270L060
Description Low Input Current High Gain LVTTL/LVCMOS Compatible 3.3 V Optocouplers
Fabricant ETC 
Logo ETC 





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HCPL-270L060 fiche technique
Agilent HCPL-270L/ 070L/273L/073L
Low Input Current High Gain
LVTTL/LVCMOS Compatible
3.3 V Optocouplers
Data Sheet
Description
These high gain series couplers use
a Light Emitting Diode and an
integrated high gain photodetector
to provide extremely high current
transfer ratio between input and
output. Separate pins for the
photodiode and output stage result
in LVTTL compatible saturation
voltages and high speed operation.
Where desired, the VCC and VO
terminals may be tied together to
achieve conventional photo-
darlington operation. A base
access terminal allows a gain
bandwidth adjustment to be
made.
These optocouplers are for use in
LVTTL/LVCMOS or other low
power applications. A 400%
minimum current transfer ratio is
guaranteed over 0 to +70˚C
operating range for only 0.5 mA
of LED current.
Functional Diagram
HCPL-270L/070L
NC 1
ANODE 2
8 VCC
7 VB
CATHODE 3
NC 4
6 VO
5 GND
HCPL-273L/073L
ANODE 1 1
CATHODE 1 2
CATHODE 2 3
ANODE 2 4
8 VCC
7 VO1
6 VO2
5 GND
Features
• Low power consumption
• High current transfer ratio
• Low input current requirements –
0.5 mA
• LVTTL/LVCMOS compatible output
• Performance guaranteed over
temperature 0˚C to +70˚C
• Base access allows gain
bandwidth adjustment
• High output current – 60 mA
• Safety approval, UL, VDE, CSA
(pending)
Applications
• Ground isolate most logic
families – LVTTL/LVCMOS
• Low input current line receiver
• High voltage insulation
• EIA RS-232C line receiver
• Telephone ring detector
• 117 V AC line voltage status
indicator – low input power
dissipation
• Low power systems – ground
isolation
TRUTH TABLE
LED
ON
OFF
VO
LOW
HIGH
SHIELD
A 0.1 µF bypass capacitor connected between pins 8 and 5 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent
damage and/or degradation which may be induced by ESD.

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