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PDF ADP3207D Data sheet ( Hoja de datos )
| Número de pieza | ADP3207D | |
| Descripción | 7-Bit Programmable Multi-Phase Mobile CPU Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
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ADP3207D
7-Bit Programmable,
Multi-Phase Mobile, CPU
Synchronous Buck
Controller
The ADP3207D is a high efficiency, multi−phase, synchronous,
buck−switching regulator controller optimized for converting
notebook battery voltage into the core supply voltage required by high
performance Intel processors. The part uses an internal 7−bit
Digital−to−Analog Converter (DAC) to read Voltage Identification
(VID) code directly from the processor that sets the output voltage.
The phase relationship of the output signals can be programmed to
provide 1−, 2−, or 3−phase operation, allowing for the construction of
up to three interleaved buck−switching stages.
The ADP3207D uses a multi−mode architecture to drive the
logic−level PWM outputs at a programmable switching frequency that
can be optimized depending on the output current requirement. The
part switches between multi−phase and single−phase operation to
maximize its effectiveness under all load conditions. In addition, the
ADP3207D includes a programmable slope function to adjust the
output voltage as a function of the load current. As a result, it is always
best positioned for a system transient.
The chip also provides accurate and reliable short−circuit
protection, adjustable current limiting, and a delayed power−good
output that accommodates On−the−Fly (OTF) output voltage changes
requested by the CPU.
The ADP3207D is specified over the extended commercial
temperature range of −10°C to 100°C and is available in a 40−lead
LFCSP.
The ADP3207DF has a soft−start time one tenth of ADP3207D.
There are no other differences between the ADP3207D and
ADP3207DF.
http://onsemi.com
LFCSP40
CASE 932AC
MARKING DIAGRAM
ADP3207D
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YYWW = Date Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 31 of this data sheet.
Features
• 1−, 2−, or 3−Phase Operation at Up to 750 kHz per Phase
• $7 mV Worst−Case Differential Sensing Error
Overtemperature
• Input Voltage Range of 3.3 V to 22 V
• Interleaved PWM Outputs for Driving External High
Power MOSFET Drivers
• Enhanced PWM FlexModet for Excellent Load
Transient Performance
• Automatic Power−Saving Modes Maximize Efficiency
During Light Load and Deeper Sleep Operation
• Soft Transient Control Reduces Inrush Current and
Audio Noise
• Active Current Balancing Between Output Phases
• Independent Current Limit and Load Line Setting
Inputs for Additional Design Flexibility
• Built−In, Power−Good Masking Supports VID OTF
• 7−Bit Digitally Programmable 0.3 V to 1.5 V Output
• Overload and Short−Circuit Protection Latchoff Delay
• Built−In, Clock Enable Output Delays CPU Clock Until
CPU Supply Voltage Stabilizes
• Current Monitor Output Signals the Total Output Power
of the Buck Converter
• This is a Pb−Free Device
Applications
• Notebook Power Supplies for Next Generation
Intel® Processors
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 0
1
Publication Order Number:
ADP3207D/D
1 page  
ADP3207D
ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 0.50 V to 1.5000 V, PSI = 1.05 V,
DPRSLP = GND, DPRSTP= 1.05 V, LLSET = CSREF, TA = −10°C to 100°C, unless otherwise noted (Note 1). RREF = 80 kW.
Current entering a pin (sunk by the device) has a positive sign.
Parameter
Symbol
Conditions
Min Typ
VOLTAGE CONTROL − Voltage Error Amplifier (VEAMP)
FB, LLINE Voltage Range
(Note 2)
VFB, VLLINE
Relative to CSREF = VDAC
−200
FB, LLINE Offset Voltage
(Note 2)
VOSVEA
Relative to CSREF = VDAC
−0.5
FB Bias Current (Note 2)
LLINE Bias Current (Note 2)
LLINE Positioning Accuracy
IFB
ILL
VFB − VVID
Measured on FB relative to VVID, LLINE
forced 80 mV below CSREF
−1.0
−50
−78
−80
COMP Voltage Range
COMP Current
VCOMP
ICOMP
Operating Range
COMP = 2.0 V, CSREF = VDAC
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
0.85
0.75
6.0
COMP Slew Rate
SRCOMP
CCOMP = 10 pF, CSREF = VDAC, Open loop
configuration
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
15
−20
Gain Bandwidth (Note 2)
GBW
VID DAC VOLTAGE REFERENCE
Non−inverting unit gain configuration,
RFB = 1 kW
20
VDAC Voltage Range
VDAC Accuracy
VFB − VVID
VDAC Differential Non−linearity (Note 2)
VDAC Line Regulation
DVFB
VDAC Boot Voltage
VBOOTFB
Soft−Start Delay (Note 2)
tDSS
Soft−Start Time
tSS
See VID Code Table
Measured on FB (includes offset), relative to
VVID, for VID table see Table 3,
TVAVI=D
−10°C to
= 1.2125
85°C
V to 1.5000
V
VVID = 0.3000 V to 1.2000 V
VCC = 4.75 V to 5.25 V
Measured during boot delay period
Measured from EN pos edge to FB = 50 mV
Measured from EN pos edge to FB settles to
VBOOT = 1.2 V within −5%
ADP3207D
ADP3207DF
0
−9.0
−7.0
−1.0
0.05
1.200
200
1.4
0.14
Boot Delay
tBOOT
Measured from FB settling to VBOOT = 1.2 V
within −5% to CLKEN neg edge
100
VDAC Slew Rate
Soft−Start ADP3207D
Soft−Start ADP3207DF
Non−LSB VID step, DPRSLP = H, Slow C4
Entry/Exit
Non−LSB VID step, DPRSLP = L, Fast C4
Exit
0.0625
0.625
0.25
1.0
FBRTN Current
IFBRTN
VOLTAGE MONITORING AND PROTECTION − Power Good
90
CSREF Undervoltage
Threshold
VUVCSREF
Relative to nominal DAC Voltage:
= 0.5125 V to 1.5 V
= 0.3 V to 0.5 V
−240
−160
−300
−300
CSREF Overvoltage
Threshold
VOVCSREF
Relative to nominal DAC Voltage
150 200
CSREF Crowbar Voltage
Threshold
VCBCSREF
Relative to FBRTN
1.65 1.7
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
Max
+200
+0.5
1.0
50
−82
4.0
1.5
+9.0
+7.0
+1.0
200
−360
−360
250
1.75
Unit
mV
mV
A
nA
mV
V
mA
V/ms
MHz
V
mV
LSB
%
V
ms
ms
ms
LSB/
ms
mA
mV
mV
V
http://onsemi.com
5
5 Page 
ADP3207D
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT
VOLTAGE
SW3
SW2
SW1
Input = 12 V
44 A to 9 A
Figure 12. Load Transient
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
SW3
SW2
SW1
Input = 12 V
2 A to 12 A
Figure 13. Single Phase Load Transient
OUTPUT
VOLTAGE
SW3
SW2
SW1
Input = 12 V
12 A to 2 A
Figure 14. Single Phase Load Transient
OUTPUT VOLTAGE
PSI
SW1
SW3
SW2
Input = 12 V
Output = 1.0 V
No Load
DPRSLP = Low
Figure 16. PSI Transition
SW3
SW2
SW1
Input = 12 V
2 A to 12 A
Figure 15. Single Phase Load Transient
OUTPUT VOLTAGE
PSI
SW1
SW3
SW2
Input = 12 V
Output = 1.0 V
No Load
DPRSLP = Low
Figure 17. PSI Transition
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11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP3207D.PDF ] | |
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