PDF HY5DU281622T-H Data sheet ( Hoja de datos )

Número de pieza	HY5DU281622T-H
Descripción	4 Banks x 2M x 16Bit Double Data Rate SDRAM
Fabricantes	Hyundai
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No Preview Available ! DESCRIPTION HY5DU281622 4 Banks x 2M x 16Bit Double Data Rate SDRAM PRELIMINARY The Hyundai HY5DU281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5DU281622 is orga- nized as 4 banks of 2,097,152x16. HY5DU281622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. Mode Register set options include the length of pipeline (CAS latency of 2 / 2.5 ), the number of consecutive read or write cycles initiated by a single control command (Burst length of 2 / 4 / 8), the burst count sequence(sequential or interleave), DQ FET Control (/QFC) and Output Driver types (Full / Half Strength Driver). Because data rate is doubled through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved than that of traditional (single data rate) Synchronous DRAM. FEATURES • 2.5V VDD and VDDQ power suppliy • All inputs and outputs are compatible with SSTL_2 interface • Delay Locked Loop(DLL) installed with DLL reset mode • Write mask byte controlled by LDM and UDM • JEDEC standard 400mil 66pin TSOP-II with 0.65mm • Bytewide data strobes by LDQS and UDQS pin pitch • Programmable CAS Latency 2 and 2.5 supported • Fully differential clock operations(CLK & CLK) with 100MHz/125MHz/133MHz • Write Operations with 1 Clock Write Latency • All addresses and control inputs except Data, Data • /QFC & Half Strength Driver controlled by EMRS strobes and Data masks latched on the rising edges • Programmable Burst Length 2 / 4 / 8 with both of the clock sequential and interleave mode • Data(DQ) and Write masks(LDM/UDM) latched on both rising and falling edges of the Data Stobe • Data outputs on LDQS/UDQS edges when read (edged DQ) Data inputs on LDQS/UDQS centers when write (centered DQ) • Internal four bank operations with single pulsed RAS • Auto refresh and self refresh supported • 4096 refresh cycles / 64ms ORDERING INFORMATION Part No. HY5DU281622(L)T-K HY5DU281622(L)T-H HY5DU281622(L)T-L * (L) Low Power Part Power Suppy VDD=2.5V VDDQ=2.5V Clock Frequency 143MHz (PC266A) 133MHz (PC266B) 125MHz (PC200) Organization Interface Package 4Banks x 2Mbit x 16 SSTL_2 400mil 66pin TSOP II JEDEC Defined Specifications compliant This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2 / Mar.00 1 page CAPACITANCE (TA=25oC, f=100MHz ) HY5DU281622 Parameter Pin Symbol Input Capacitance A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS, CAS, WE Clock Capacitance CLK, CLK Data Input / Output Capacitance DQ0 ~ DQ15, LDQS, UDQS, LDM, UDM CIN CCLK CIO Min 2.0 2.0 4.0 Max 3.0 3.0 5.0 Unit pF pF pF Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT VTT VTT RT=50Ω RT=50Ω Output RS=25Ω Zo=50Ω CL=30pF VREF Rev. 1.2 / Mar.00 5 5 Page

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