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PDF LM1270 Data sheet ( Hoja de datos )

Número de pieza LM1270
Descripción Hi-Brite 200 MHz I2C Compatible RGB Image Enhancer
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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May 2003
LM1270
Hi-Brite 200 MHz I2C Compatible RGB Image Enhancer
with Video Auto Sizing
General Description
The LM1270 is a supplementary IC to the low cost chipset
(LCCS). It modifies the video stream prior to the LCCS
preamplifier. The key function of the LM1270 is image pro-
cessing for enhancing pictures or motion video. Image en-
hancement is accomplished by special intermediate fre-
quency boosting. 200 MHz bandwidth assures minimal
impact on the video change when adding the LM1270.
Other functions of the LM1270 are:
1. Measures the length of the active video and its front
porch time with respect to the horizontal flyback and
vertical sync for auto alignment information.
2. Calibration mode for determining the start of the image
coordinates.
3. Data receiver for receiving data encoded on video.
4. Window highlight with respect to the horizontal and ver-
tical sync, used with the image enhancing feature.
5. Video source selection, allowing the choice of two ana-
log inputs.
Features
n Ideal companion IC to the LCCS to provide image
enhancing for viewing pictures or motion video
n Programmable clamp generator
n Programmable blank generator
n Video detection controlled by I2C compatible bus,
allowing easy and accurate Hi-Brite window calibration
n Programmable window Hi-Brite function
n Programmable image sharpness control (TV emphasis),
adjustable for different line rates
n Measures video position with respect to the horizontal
flyback and vertical sync pulses, providing necessary
information for auto-sizing
n Emphasis done either inside or outside the window
Applications
n Any monitor designed with the LCCS chip set
n Standard 0.7V video output assures compatibility with
any video pre-amp
Block and Connection Diagram
FIGURE 1. Order Number LM1270N
See NS Package Number N24D
© 2003 National Semiconductor Corporation DS200635
20063501
www.national.com

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LM1270 pdf
Pin Descriptions
Pin
Pin Name
No.
1 Blue 1 Video In
2 Red 1 Video In
3 Green 1 Video In
Schematic
4 Analog Input
Ground
5 Blue 2 Video In
6 Red 2 Video In
7 Green 2 Video In
8 Digital Ground
10 PLL VCC
9 PLL Filter
11 V Sync
Description
Channel 1 video inputs. These inputs must be AC
coupled with a 0.1 µF cap. DC restoration is done at
these inputs. A series resistor of about 33and
external ESD protection diodes should also be used.
Channel 1 video passes through the emphasis
section used for the Hi-Brite window. When using
Hi-Brite the channel 1 input pin must be shorted to
the corresponding channel 2 input pin.
Ground Pin for the input analog circuits of the
LM1270
Channel 2 video inputs. These video inputs must be
AC coupled with a 0.1 µF cap. DC restoration is
done at these inputs. A series resistor of about 33
and external ESD protection diodes should also be
used. When using Hi-Brite the channel 2 input pin
must be shorted to the corresponding channel 1
input pin.
The ground pin should be connected to the rest of
the circuit ground by a short but independent PCB
trace to prevent contamination by extraneous
signals. The VCC pin should be isolated from the
rest of the VCC line by a ferrite bead and bypassed
to pin 8 with an electrolytic capacitor and a high
frequency ceramic.
Recommended topology and values are shown to
the left. It is recommended that both filter branches
be bypassed to the independent ground as close to
pin 8 as possible. Great care should be taken to
prevent external signals from coupling into this filter
from video, I2C compatible bus, etc.
Logic level vertical sync signal received from the
video card in the PC or sync stripper circuit.
5 www.national.com

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LM1270 arduino
Video Detection (Continued)
sate for clocking delays in the timing counters in the
LM1270. This value is empirically derived from testing the
video system.
VIDEO INPUT DETECTION
The outputs of the three video detector channels are OR’d
together to provide a single composite signal of the three
channels when used for timing parameter measurement.
The video detect logic must find the extreme points of the
displayed image during each frame with respect to the hori-
zontal and vertical flyback pulses as measured using the
internal PLL. For best performance in autosizing mode, it is
recommended that the application use the maximum number
of pixels per line when measurements are made. Remem-
ber, the VCO frequency is limited to 160 MHz when the
prescaler is set to 7.
The durations to be measured are shown generically in the
figures below, and apply to both horizontal and vertical tim-
ings. For the horizontal timings the measurements will de-
pend on the mode selected in the EMPHASIS register. Ver-
tical and HFLYBACK timing measurements will be the same
in both modes.
20063521
FIGURE 4. Timing Intervals with WCHE = 1
20063522
FIGURE 5. Timing Intervals with WCHE = 0
1. Flyback or sync period: the duration of either the sync
input or the horizontal flyback, in either horizontal lines
(vertical) or pixels (horizontal).
2. Back porch period: the duration between the trailing
edge of the sync or flyback pulse and the leading edge
of the first detected video, in either lines (vertical) or
pixels (horizontal).
3. Video period: the duration between the leading edge of
the first detected video and the trailing edge of the last
detected video, in either lines (vertical) or pixels (hori-
zontal).
4. Front porch: the duration between the trailing edge of
the last detected video and the leading edge of the sync
or flyback pulse, in either lines (vertical) or pixels (hori-
zontal).
Note: In the horizontal timing measurement description, reference to sync
means either HSYNC or H_FEEDBACK, selected by WCHE bit in the
EMPHASIS register.
As the video may start and finish at different positions on the
screen, depending upon the image, the measured horizontal
porches and video time may vary from line to line. To over-
come this, the periods should be measured over at least one
entire field. The hardware records the shortest back porch
and front porch periods used over the measured period.
WINDOW COORDINATE DATA
The microcontroller must program the highlight window co-
ordinates in the LM1270 by writing to the appropriate regis-
ters. The coordinate values must be sent from the PC. For
maximum flexibility, the LM1270 is designed to allow opera-
tion such that the coordinate data may be sent by:
1. DDC2A/B (e.g., I2C compatible) transmission
2. Information carried as video data during the vertical
blanking time
3. Any other PC-monitor interface (e.g., USB)
COORDINATE DATA TRANSMISSION BY VIDEO
OPERATION
When sending coordinate data by video please refer to the
information for register 27 in the register descriptions. Any
video line may be selected for data, clock, or window. It is
important to make sure each video line has a different se-
lection otherwise the video transmission of data will not
function. It is possible to program two video channels to
carry the same information and create this incorrect opera-
tion.
If the LIMIT bit of the TEST1 register is set to a “1” (default
value), then one line of data may be transmitted after the
vertical sync on one of the video channels. This data must be
sent during the vertical blanking time that is set by the
vertical blanking register. Data must be transmitted only
during the vertical blanking time otherwise it will be ignored
by the logic. If the LIMIT bit of the TEST1 register is set to a
“0”, then the data may be transmitted at any time following
the vertical sync.
The data consists of a stream of 9 bytes. In normal use it is
expected that the first eight bytes will be data, and the
remaining byte will be used as a checksum. Alternatively, the
ninth byte may be used as an additional data byte.
Another video channel provides a clock pulse stream of
exactly 72 pulses. The logic counts the number of pulses
between two horizontal sync pulses. If the number of clock
pulses is greater or less than 72, then the data is ignored. If
the count is 72, then the data is shifted into registers 2E-36
upon arrival of the next horizontal sync, provided the output
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