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PDF LM1276 Data sheet ( Hoja de datos )
| Número de pieza | LM1276 | |
| Descripción | 150 MHz I2C Compatible RGB Preamplifier | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 2005
LM1276
150 MHz I2C Compatible RGB Preamplifier with Internal
512 Character OSD ROM, 512 Character RAM and 4
DACs
General Description
The LM1276 pre-amp is an integrated CMOS CRT preamp
with an integrated Hi-Brite Window generator, 512 Character
OSD generator, and an auto size measurement circuit. It has
an I2C compatible interface, which allows control of all the
parameters necessary to directly setup and adjust the gain
and contrast in the CRT display. Brightness and bias can be
controlled through the DAC outputs, which are well matched
to the LM2479 and LM2480 integrated bias clamp ICs. The
LM1276 preamp is also designed to be compatible with the
LM247x high gain driver family.
Black level clamping of the video signal is carried out directly
on the AC coupled input signal into the high impedance
preamplifier input, thus eliminating the need for additional
clamp capacitors. Horizontal and vertical blanking of the
outputs is provided. Vertical blanking is optional and its
duration is register programmable.
The IC is packaged in an industry standard 28-lead narrow
DIP molded plastic package.
Features
n Integrated Hi-Brite Window Generator operation
independent of the Microcontroller.
n Programmable Video Emphasis Control.
n 8 Programmable Hi-Brite Windows.
n Hi-Brite Enhancement on full screen, window only, or
outside of windows.
n Fully addressable 512 Character OSD.
n Internal 512 character OSD ROM usable as either (a)
384 2-color plus 128 4-color characters, (b) 640 2-color
characters, or (c) some combination in between.
n Internal 512 character RAM.
n Enhanced I2C compatible microcontroller interface to
allow versatile Page RAM access.
n OSD Window Fade In/Fade Out.
n OSD Variable Tone Transparency.
n 3 Bit OSD Contrast.
n Video Data detection for Auto Centering & Sizing.
n 2 Bit Adjustable Burn-in screen Mode with no video
input.
n 4 DAC outputs (8-bit resolution) for bus controlled CRT
bias and brightness.
n Spot killer, which blanks the video outputs when VCC
falls below the specified threshold.
n Suitable for use with discrete or integrated clamp, with
software configurable brightness mixer.
n Programmable ABL Onset for Multi-Limit Applications.
n 4-Bit Programmable start position for internal Horizontal
Blanking.
n Horizontal blanking and OSD synchronization directly
from deflection signals. The blanking can be disabled, if
desired.
n Vertical blanking and OSD synchronization directly from
sync signals. The blanking width is register
programmable and can be disabled, if desired.
n Power Saving Mode with 65% power reduction.
n Matched to LM246x, LM247x drivers, and LM2479/80
bias IC’s.
Applications
n Ideal preamplifier IC for total Hi-Brite Solution.
n 17" and 19” bus controlled monitors with OSD.
n Low cost systems with LM247x drivers.
© 2005 National Semiconductor Corporation DS200969
www.national.com
1 page  
Video Signal Electrical Characteristics (Continued)
Unless otherwise noted: TA = 25˚C, VCC = +5.0V, VIN = 0.70 VP-P, VABL = VCC, CL = 8 pF, Video Outputs = 2.0 VP-P. Setting
numbers refer to the definitions in Table 1. See (Note 7) for Min and Max parameters and (Note 6) for Typicals.
Symbol
Parameter
Conditions
Min Typ Max Units
AV G-50%
AV G-Min
AV Match
Gain Attenuation @ 50%
Maximum Gain Attenuation
Maximum Gain Match between
Channels
Test Setting 6, AC input signal.
Test Setting 7, AC input signal.
Test Setting 3, AC input signal.
−4.0
−11
±0.5
dB
dB
dB
AV Track
Gain Change between Channels
Tracking when changing from Test
Setting 8 to Test Setting 5. See (Note
11).
±0.5
dB
VidThreshold
VABL TH
Video Threshold
ABL Control Range Upper Limit
Normal Operation
(Note 12), Test Setting 4, AC input
signal.
80 mV
4.8 V
VABL Range
ABL Gain Reduction Range
(Note 12), Test Setting 4, AC input
signal.
2.8 V
AV 3.5/AV Max
AV 2.0/AV Max
IABL Max
ABL Gain Reduction at 3.5V
(Note 12), Test Setting 4, AC input
signal. VABL = 3.5V
ABL Gain Reduction at 2.0V
(Note 12), Test Setting 4, AC input
signal. VABL = 2.0V
ABL Input Current Sink Capability (Note 12), Test Setting 4, AC input
signal.
−2 dB
−12 dB
2.5 mA
VABL Max
AV ABL Track
Maximum ABL Input Voltage
during Clamping
ABL Gain Tracking Error
(Note 12), Test Setting 4, AC input
signal. IABL = IABL MAX
(Note 9), Test Setting 4, 0.7 VP-P
input signal, ABL voltage set to 4.5V
and 2.5V.
VCC +
0.1
V
5.0 %
RIP Minimum Input Resistance (pins Test Setting 4.
5, 6, 7)
20 MΩ
OSD Electrical Characteristics
Unless otherwise noted: TA = 25˚C, VCC = +5.0V. See (Note 7) for Min and Max parameters and (Note 6) for Typicals.
Symbol
Parameter
Conditions
Min Typ Max
VOSDHIGH max
Maximum OSD Level with OSD
Contrast 111
Palette Set at 111, OSD Contrast =
111, Test Setting 3
3.02
VOSDHIGH 110
Maximum OSD Level with OSD
Contrast 110
Palette Set at 111, OSD Contrast =
110, Test Setting 3
2.91
VOSDHIGH 101
Maximum OSD Level with OSD
Contrast 101
Palette Set at 111, OSD Contrast =
01, Test Setting 3
2.79
VOSDHIGH 100
Maximum OSD Level with OSD
Contrast 100
Palette Set at 111, OSD Contrast =
100, Test Setting 3
2.67
VOSDHIGH 011
Maximum OSD Level with OSD
Contrast 011
Palette Set at 111, OSD Contrast =
011, Test Setting 3
2.55
VOSDHIGH 010
Maximum OSD Level with OSD
Contrast 010
Palette Set at 111, OSD Contrast =
010, Test Setting 3
2.43
VOSDHIGH 001
Maximum OSD Level with OSD
Contrast 001
Palette Set at 111, OSD Contrast =
001, Test Setting 3
2.32
VOSDHIGH 000
Maximum OSD Level with OSD
Contrast 000
Palette Set at 111, OSD Contrast =
000, Test Setting 3
2.20
∆VOSD (Black)
Difference between OSD Black
Register 0x8438=0x18, Input Video
Level and Video Black Level (same = Black, Same Channel, Test
±130
channel)
Setting 8
Units
V
V
V
V
V
V
V
V
mV
5 www.national.com
5 Page 
Typical Performance
Characteristics VCC = 5V, TA = 25˚C unless
otherwise specified (Continued)
SYSTEM INTERFACE SIGNALS
The Horizontal Sync, Flyback, Vertical Sync, and the Clamp
input signals are important for proper functionality of the
LM1276. Both blanking inputs must be present for OSD
synchronization. In addition, the Horizontal blanking input
also assists in setting the proper cathode black level, along
with the Clamping pulse. The Vertical blanking input initiates
a blanking level at the LM1276 outputs, which is program-
mable from 3 to 127 lines (at least 10 is recommended). This
input is set up to only accept a vertical sync pulse, and the
leading edge is used to start the programmable vertical
blanking signal directly. The start position of the internal
Horizontal blanking pulse is programmable from 0 to 64
pixels ahead of the start position of the Horizontal flyback
input. Both horizontal and vertical blanking can be individu-
ally disabled, if desired.
Figure 3 and Figure 4 show the Horizontal Flyback input
when it is logic level and the Vertical input (which must
always be logic level). Figure 3 shows the smaller pin 28
voltage superimposed on the horizontal blanking pulse input
to the neck board with RH = 4.7k and C1 = 0.1 µF. Note
where the voltage at pin 28 is clamped to about 1V when the
pin is sinking current. Figure 4 shows the smaller pin 1
voltage superimposed on the vertical blanking input to the
neck board with RV = 4.7k. These component values corre-
spond to the application circuit of Figure 9.
Please note that the Horizontal Flyback signal to pin 28
MUST be continuously provided to the IC, even during en-
ergy save or sleep modes. In the application, this signal
should be always generated whether the VGA cable is dis-
connected, the monitor is in energy save mofe, or sleep
mode.
Figure 5 show the case where the horizontal input is from
deflection. Figure 5 shows the pin 28 voltage which is de-
rived from a horizontal flyback pulse of 35V peak to peak
with RH = 8.2K and C1 jumpered.
Figure 6 shows the pin 27 clamp input voltage superimposed
on the neck board clamp logic input pulse. R = 1k and should
be chosen to limit the pin 27 voltage to about 2.5V peak to
peak. This corresponds to the application circuit given in
Figure 9. The clamp input pin can also be internally con-
nected to the Horizontal Sync pin, thus eliminating the need
for a Clamp signal supplied to the neckboard. This can be
enabled with register 0x853E[4].
H SYNC & V SYNC
V Sync at pin 1 and H Sync at pin 15 must be supplied with
logic level signals generated by the MCU. In an application
where a logic level clamp pulse is used, the same signal can
be used for the H Sync input. It is important that both V Sync
and H Sync are always receiving signals, even during VGA
cable disconnect, energy save mode, or sleep mode.
CATHODE RESPONSE
Figure 7 shows the response at the red cathode for the
application circuit in Figures 9, 10. The input video rise time
is 1.5 ns. The resulting leading edge has a 7.1 ns rise time
and 7.6% overshoot, while the trailing edge has a 7.1 ns rise
time and 6.9% overshoot using an LM2467 driver.
ABL GAIN REDUCTION
The ABL function reduces the contrast level of the LM1276
as the voltage on pin 26 is lowered from VCC to around 2V.
Figure 8 shows the amount of gain reduction as the voltage
is lowered from VCC (5.0V) to 2V. The gain reduction is small
until V26 reaches the knee around 3.7V, where the slope
increases. Many system designs will require about 3 dB to
5 dB of gain reduction in full beam limiting. Additional attenu-
ation is possible, and can be used in special circumstances.
However, in this case, video performance such as video
linearity and tracking between channels will tend to depart
from normal specifications.
The onset of ABL in the LM1276 is adjustable so that the
amount of beam limiting can be varied, especially for larger
Hi-Brite window displays where the contrast level is not
desired to be reduced as much as a normal video display.
The beam current limiting is 4-bit adjustable in steps of 80 µA
each all the way up to a delta of 1.2 mA. The value of the
ABL pull up resistor (R2) to the external +80V supply must
be selected carefully such that the ABL threshold current will
be at the desired maximum (i.e. 2 mA) when register 0x85C4
is at the lowest setting, 0x00.
There are 4 different ABL current registers corresponding to
4 different ABL settings. Each setting or register (0x85C4 -
0x85C7) can be assigned a different ABL current threshold.
ABL current register 0 can correspond to a minimal area of
the screen being highlighted, and ABL current register 4 can
correspond to the maximum area of the screen being high-
lighted. This area is calculated by the HiBrite software, and
the particular ABL register that is is to be activated is se-
lected by the software. The values of each register are
written by the MCU.
11 www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LM1276.PDF ] | |
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