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PDF PCF8536BT Data sheet ( Hoja de datos )
| Número de pieza | PCF8536BT | |
| Descripción | Universal LCD driver | |
| Fabricantes | NXP Semiconductors | |
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PCF8536
Universal LCD driver for low multiplex rates including a 6
channel PWM generator
Rev. 2 — 21 February 2012
Product data sheet
1. General description
The PCF8536 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD)1 with low multiplex rates. It generates the drive signals for any multiplexed LCD
containing up to eight backplanes, up to 44 segments, and up to 320 elements. The
PCF8536 is compatible with most microcontrollers and communicates via the two-line
bidirectional I2C-bus (PCF8536AT) or a three line unidirectional SPI-bus (PCF8536BT).
Communication overheads are minimized using a display RAM with auto-incremented
addressing.
The PCF8536 features an on-chip PWM controller for LED illumination. Up to six
independent channels can be configured. Each channel has 128 levels allowing the
possibility for two RGB controllers. Each of them provides over 2 million colors. Each
channel can also be used for static drive.
2. Features and benefits
Single-chip 320 segment LCD controller and driver with 6 channel PWM generator
6 channel PWM generator for backlight LED illumination
Selectable display bias configuration
Wide range for digital power supply: from 1.8 V to 5.5 V
Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 9.0 V for high
threshold twisted nematic LCDs
Low power consumption
Selectable backplane drive configuration: 4, 6, or 8 backplane multiplexing
LCD and logic supplies may be separated
320-bit RAM for display data storage
6 PWM outputs with a 7-bit resolution (128 steps) and drivers for external transistors
Programmable PWM frame frequency to avoid LCD backlight flickering
400 kHz I2C-bus interface (PCF8536AT)
5 MHz SPI-bus interface (PCF8536BT)
Programmable frame frequency in the range of 60 Hz to 300 Hz in steps of 10 Hz;
factory calibrated
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.
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7. Pinning information
7.1 Pinning
S9 1
S10 2
S11 3
S12 4
S13 5
S14 6
S15 7
S16 8
S17 9
S18 10
S19 11
BP0/S32 12
BP1/S33 13
BP2/S34 14
BP3/S35 15
BP4/S43/S36 16
BP5/S42/S37 17
BP6/S41/S38 18
BP7/S40/S39 19
S20 20
S21 21
S22 22
S23 23
S24 24
S25 25
S26 26
S27 27
S28 28
PCF8536AT
56 S8
55 S7
54 S6
53 S5/GP5
52 S4/GP4
51 S3/GP3
50 S2/GP2
49 S1/GP1
48 S0/GP0
47 VLCD
46 OSCCLK
45 VDD
44 VSS
43 RESET
42 SDA
41 SCL
40 A0
39 S39/BP0
38 S38/BP1
37 S37/BP2
36 S36/BP3
35 S35/BP4/S43
34 S34/BP5/S42
33 S33/BP6/S41
32 S32/BP7/S40
31 S31
30 S30
29 S29
013aaa430
Top view. For mechanical details, see Figure 51.
Fig 3. Pin configuration for TSSOP56 (PCF8536AT)
S9 1
S10 2
S11 3
S12 4
S13 5
S14 6
S15 7
S16 8
S17 9
S18 10
S19 11
BP0/S32 12
BP1/S33 13
BP2/S34 14
BP3/S35 15
BP4/S43/S36 16
BP5/S42/S37 17
BP6/S41/S38 18
BP7/S40/S39 19
S20 20
S21 21
S22 22
S23 23
S24 24
S25 25
S26 26
S27 27
S28 28
PCF8536BT
56 S8
55 S7
54 S6
53 S5/GP5
52 S4/GP4
51 S3/GP3
50 S2/GP2
49 S1/GP1
48 S0/GP0
47 VLCD
46 OSCCLK
45 VDD
44 VSS
43 RESET
42 SDI
41 SCL
40 CE
39 S39/BP0
38 S38/BP1
37 S37/BP2
36 S36/BP3
35 S35/BP4/S43
34 S34/BP5/S42
33 S33/BP6/S41
32 S32/BP7/S40
31 S31
30 S30
29 S29
013aaa431
Top view. For mechanical details, see Figure 51.
Fig 4. Pin configuration for TSSOP56 (PCF8536BT)
5 Page 
NXP Semiconductors
PCF8536
Universal LCD low multiplex driver with 6 channel PWM generator
Table 9. Effect of the power-down bit (PD)
Effect on function Mode settings
Effect of setting PD
0
backplane output
E=1
normal function
segment output
E=1
normal function
internal oscillator
OSC = 0, COE = 1
on
OSCCLK pin
OSC = 0, COE = 1
output of internal
oscillator frequency
OSCCLK pin
OSC = 1
input clock
GPO
GPO
static drive
PWM drive
static drive
PWM drive
1
VSS
VSS
off
VDD
clock input, can be
logic 0, logic 1, or left
floating
static drive
static drive
With the following sequence, the PCF8536 can be set to a state of minimum power
consumption, called power-down mode.
START
Disable display
by setting bit E
logic 0
External clock
can be
removed now
Enable power-
down mode
with PD = 1
PCF8536
Product data sheet
STOP
013aaa447
Fig 6. Recommended power-down sequence
Remarks:
• It is necessary to run the power-down sequence before removing the supplies.
Depending on the application, care must be taken that no other signals are present at
the chip input or output pins when removing the supplies (see Section 10). Otherwise
it may cause unwanted display artifacts. In case of an uncontrolled removal of supply
voltages, the PCF8536 will not be damaged.
• Static voltages across the liquid crystal display can build up when the external LCD
supply voltage (VLCD) is on while the IC supply voltage is off, or vice versa. This may
cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be
applied or removed together.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 21 February 2012
© NXP B.V. 2012. All rights reserved.
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