PDF PA5388 Data sheet ( Hoja de datos )

Número de pieza	PA5388
Descripción	192 kHz Stereo Audio CODEC
Fabricantes	Protek Devices
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No Preview Available ! ANALOG PRODUCTS DIVISION PA5388 100dB, 24-Bit, 192 kHz Stereo Audio CODEC FEATURES GENERAL DESCRIPTION ADC 24-bit, 8 kHz to 96 kHz sampling frequency 95 dB dynamic range, 95 dB signal to noise ratio, -85 dB THD+N Stereo or mono microphone interface with microphone amplifier Auto level control and noise gate 3-to-1 analog input selection Various analog input mixing and gains DAC 24-bit, 8 kHz to 96 kHz sampling frequency 96 dB dynamic range, 96 dB signal to noise ratio, -83 dB THD+N 40 mW headphone amplifier, pop noise free Stereo enhancement Bass and Treble Various analog output mixing and gains LOW POWER 1.8V to 3.3V operation 7 mW playback; 16 mW playback and record SYSTEM I2C or SPI µC interface 256Fs, 384Fs, USB 12 MHz or 24 MHz Master or slave serial port I2S, Left Justified, DSP/PCM Mode The PA5388 is a high performance, low power and low cost audio CODEC. It consists of 2-ch ADC, 2-ch DAC, microphone amplifier, headphone amplifier, digital sound effects, and analog mixing and gain functions. The device uses advanced multi-bit delta-sigma modulation technique to convert data between digital and analog. The multi-bit delta-sigma modulators make the device with low sensitivity to clock jitter and low out of band noise. The PA5388 is pin to pin compatible to WM8988 except Pin9 ALRCK and Pin25 DACREF. See the Pin Configuration Table. BLOCK DIAGRAM APPLICATIONS GPS Bluetooth MP3, MP4, PMP Cell phone Digital camera, camcorder Portable audio devices LIN1 LIN2 LIN1 LIN2 micL MIC AMP micL+micR LIN1-RIN1 LIN2-RIN2 micL+micR RIN1 RIN2 micR MIC AMP LIN1-RIN1 RIN1 RIN2 LIN LIN RIN DACL DACR Stereo Enhanced ALC ADC DAC RIN DACL DACR LIN RIN DACL DACR LIN2-RIN2 Clock Manager µC Interface + mixL mixL mixR mixL +/-mixR + mixR LOUT1 ROUT1 LOUT2 ROUT2 Serial Audio Data ORDERING INFORMATION Temperature Range Package -40 to 85 °C QFN-28 Part Number PA5388-T7 561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 95256 Rev.0. 05/10 www.protekanalog.com NOT FOR USE IN LIFE SUPPORT SYSTEMS 1 page ANALOG PRODUCTS DIVISION PA5388 100dB, 24-Bit, 192 kHz Stereo Audio CODEC LRCK Input SLCK Input SDOUT SDIN tslr tsdo tsclkh tsclkl tsclkw tsdis tsdih Serial Audio Port Timing SERIAL CONTROL PORT SWITCHING SPECIFICATIONS PARAMETER SPI Mode SPI_CLK clock frequency SPI_CLK edge to SPI_CSn falling SPI_CSn High Time Between transmissions SPI_CSn falling to SPI_CLK edge SPI_CLK low time SPI_CLK high time SPI_DIN to SPI_CLK rising setup time SPI_CLK rising to DATA hold time 2-wire Mode SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL Fall Time SCL Symbol TSPICS TSPISH TSPISC TSPICL TSPICH TSPIDS TSPIDH FSCL TTWID TTWSTH TTWCL TTWCH TTWSTS TTWDH TTWDS TTWR TTWF MIN 5 500 10 45 45 10 15 4.7 4.0 4.0 4.0 4.7 0.1 100 MAX 10 100 25 25 UNIT MHz ns ns ns ns ns ns ns KHz us us us us us us ns us ns 561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 95256 Rev.0. 05/10 www.protekanalog.com NOT FOR USE IN LIFE SUPPORT SYSTEMS 5 Page ANALOG PRODUCTS DIVISION PA5388 100dB, 24-Bit, 192 kHz Stereo Audio CODEC Reg. 23 DACLRSWAP DACLRP DACWL DACFORMAT Reg. 24 DACFsMode DACFsRatio Reg. 25 DACRampRate DACSoftRamp DACZeroCrs DACLeR DACMute AutoMute Reg. 26 DACVolumeL (LDACVOL) Reg. 27 DACVolumeR (RDACVOL) Reg. 28 DeemphasisMode DAC_invL DAC_invR ClickFree Reg. 29 ZeroL ZeroR Mono SE Vpp_scale Reg. 30 Shelving_a[29:24] Reg. 31 Shelving_a[23:16] Reg. 32 Shelving_a[15:8] Reg. 33 Shelving_a[7:0] Reg. 34 Shelving_b[29:24] Reg. 35 Shelving_b[23:16] Reg. 36 Shelving_b[15:8] Reg. 37 Shelving_b[7:0] Reg. 38 LMIXSEL RMIXSEL Reg. 39 LD2LO LI2LO LI2LOVOL Reg. 40 RD2LO RI2LO RI2LOVOL Reg. 41 LD2RO LI2RO LI2ROVOL Reg. 42 RD2RO RI2RO RI2ROVOL Reg. 43 LD2MO LI2MO LI2MOVOL Reg. 44 RD2MO RI2MO RI2MOVOL Reg. 45 ROUT2INV OUT3SW VROI HPSWEN HPSWPOL MOUTINV Reg. 46 LOUT1VOL Reg. 47 ROUT1VOL Reg. 48 LOUT2VOL Reg. 49 ROUT2VOL Reg. 50 MONOOUTVOL Reg. 51 hpLout1_ref1 hpLout1_ref2 hpRout1_ref1 hpRout1_ref2 hpOut3_ref1 hpOut3_ref2 hpMono_ref1 hpMono_ref2 Reg. 52 spkLout2_ref1 spkLout2_ref2 spkRout2_ref1 spkRout2_ref2 mixer_ref1 mixer_ref2 MREF1 MREF2 CHIP CONTROL AND POWER MANAGEMENT Register 0 – Chip Control 1, Default 0000 0110 Bit Name Bit Description SCPReset LRCM DACMCLK 7 0 – normal (default) 1 – reset control port register to default 6 0 – ALRCK disabled when both ADC disabled; DLRCK disabled when both DAC disabled (default) 1 – ALRCK and DLRCK disabled when all ADC and DAC disabled 5 0 – when SameFs=1, ADCMCLK is the chip master clock source (default) 1 – when SameFs=1, DACMCLK is the chip master clock source 561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 632-1715 95256 Rev.0. 05/10 www.protekanalog.com NOT FOR USE IN LIFE SUPPORT SYSTEMS 11 Page

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