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PDF PCF8523TK Data sheet ( Hoja de datos )
| Número de pieza | PCF8523TK | |
| Descripción | Real-Time Clock (RTC) and calendar | |
| Fabricantes | NXP Semiconductors | |
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PCF8523
Real-Time Clock (RTC) and calendar
Rev. 3 — 30 March 2011
Product data sheet
1. General description
The PCF8523 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power
consumption. Data is transferred serially via an I2C-bus with a maximum data rate of
1000 kbit/s. Alarm and timer functions are available with the possibility to generate a
wake-up signal on an interrupt pin. An offset register allows fine-tuning of the clock. The
PCF8523 has a backup battery switch-over circuit, which detects power failures and
automatically switches to the battery supply when a power failure occurs.
2. Features and benefits
Provides year, month, day, weekday, hours, minutes, and seconds based on a
32.768 kHz quartz crystal
Resolution: seconds to years
Clock operating voltage: 1.0 V to 5.5 V
Low backup current: typical 150 nA at VDD = 3.0 V and Tamb = 25 C
2 line bidirectional 1 MHz Fast-mode Plus (Fm+) I2C interface
Battery backup input pin and switch-over circuit
Freely programmable timer and alarm with interrupt capability
Selectable integrated oscillator load capacitors for CL = 7 pF or CL = 12.5 pF
Internal Power-On Reset (POR)
Open-drain interrupt or clock output pins
Programmable offset register for frequency adjustment
3. Applications
Time keeping application
Battery powered devices
Metering
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.
1 page  
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
OSCI
2
OSCO
3
1 VDD
12 INT1/CLKOUT
11 n.c.
VBAT
4
PCF8523U
10 SCL
VSS 5
n.c. 6
9 SDA
INT2
7
8 CLKOUT
013aaa317
Viewed from active side. For mechanical details, see Figure 39 on page 55.
Fig 5. Pin configuration for PCF8523U
7.2 Pin description
Table 3.
Symbol
OSCI
Pin description
Pin
SO8
(PCF8523T)
1
OSCO
2
n.c. -
VBAT
VSS
INT2
3
4
-
CLKOUT
-
SDA
5
SCL 6
INT1/CLKOUT 7
VDD
8
Type
Description
TSSOP14 HVSON8
PCF8523U
(PCF8523TS) (PCF8523TK)
1
1
2
input
oscillator input;
high-impedance node[1]
2
2
3
output
oscillator output;
high-impedance node[1]
3, 6, 9, 12[2] -
6 and 11[2] -
not connected; do not connect
and do not use it as feed through
4
3
4
supply
battery supply voltage
5
4[3]
5[4]
supply
ground supply voltage
7-
7
output
interrupt 2 (open-drain, active
LOW)
8-
8
output
clock output (open-drain)
10 5
9 input/output serial data input/output
11 6
10
input
serial clock input
13 7
12
output
interrupt 1/clock output
(open-drain)
14 8
1
supply
supply voltage
[1] Wire length between quartz and package should be minimized.
[2] For manufacturing tests only; do not connect it and do not use it.
[3] The die paddle (exposed pad) is connected to VSS and should be electrically isolated.
[4] The substrate (rear side of the die) is connected to VSS and should be electrically isolated.
PCF8523
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 30 March 2011
© NXP B.V. 2011. All rights reserved.
5 of 66
5 Page 
NXP Semiconductors
PCF8523
Real-Time Clock (RTC) and calendar
8.3 Reset
A reset is automatically generated at power-on. A reset can also be initiated with the
software reset command. Software reset command means setting bits 6, 4, and 3 in
register Control_1 (00h) logic 1 and all other bits logic 0 by sending the bit sequence
01011000 (58h), see Figure 7.
slave address
R/W
address 00h
software reset 58h
SDA s 1 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 A 0 1 0 1 1 0 0 0 A P/S
SCL
internal
reset signal
Fig 7. Software reset command
013aaa320
PCF8523
Product data sheet
Table 8. Register reset values
Bits labeled X are undefined at power-on and unchanged by subsequent resets. Bits labeled - are
not implemented.
Address Register name
Bit
76543210
00h Control_1
00000000
01h Control_2
00000000
02h Control_3
111-
0000
03h Seconds
1 XXXXXXX
04h Minutes
- XXXXXXX
05h Hours
- - XXXXXX
06h Days
- - XXXXXX
07h Weekdays
- - - - - XXX
08h Months
- - - XXXXX
09h Years
XXXXXXXX
0Ah Minute_alarm
1 XXXXXXX
0Bh Hour_alarm
1-
XXXXXX
0Ch Day_alarm
1-
XXXXXX
0Dh Weekday_alarm 1 - - - - X X X
0Eh Offset
00000000
0Fh Tmr_CLKOUT_ctrl 0 0 0 0 0 0 0 0
10h
Tmr_A_freq_ctrl
-
-
-
-
-
111
11h Tmr_A_reg
XXXXXXXX
12h
Tmr_B_freq_ctrl
-
000-
111
13h Tmr_B_reg
XXXXXXXX
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 30 March 2011
© NXP B.V. 2011. All rights reserved.
11 of 66
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