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PDF EMP8046-50VB03NRR Data sheet ( Hoja de datos )
| Número de pieza | EMP8046-50VB03NRR | |
| Descripción | 50mA Ultra-Low Quiescent Current LDO Linear Regulator | |
| Fabricantes | Elite Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de EMP8046-50VB03NRR (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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ESMT/EMP
Preliminary
EMP8046
50mA Ultra-Low Quiescent Current
LDO Linear Regulator
General Description
The EMP8046 is a positive voltage regulator with high
accuracy output voltage and ultra-low quiescent
current which is typically 1.0μA. The device is ideal
for battery powered handheld equipments which
require low quiescent current.
Applications
g Battery power equipments
g Portable communication devices
g Precision voltage references
g Hand-Held electronics
g Wireless communication systems
The EMP8046 contains a bandgap voltage
reference, an error amplifier, a P-channel pass
transistor, and a resistor-divider for setting output
voltage. The output voltage is fixed with high
accuracy by advanced trimming technology.
The EMP8046 has been designed to be used with low
cost ceramic capacitors and requires a minimum
output capacitor of 1.0μF. The devices are available
in SOT-23-3 and SOT-89-3 packages.
Features
g Operating voltages range: 2.5V to 18V
g Maximum output current: 100mA
g Low dropout: 800mV @ 50mA
g ±2% output voltage tolerance
g Low ESR capacitor compatible
g RoHS compliant and 100% Lead(Pb)-free and
green (halogen free with commercial
standard)
Typical Application
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Dec. 2011
Revision: 0.2
1/12
1 page  
ESMT/EMP
Preliminary
EMP8046
Note 1: Absolute maximum ratings indicate limits beyond which damage may occur.
Note 2: All voltages are in respect to the potential of the ground pin.
Note 3: θJA is measured in the natural convection at TA=25℃ on a high effectively thermal conductivity test board (2
layers, 2S0P).
Note 4: θJC represents the resistance between the chip and the top of the package case.
Note 5: Maximum power dissipation for the device is calculated using the following equation:
PD
=
TJ(MAX)
θJA
-
TA
Where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the
junction-to-ambient thermal resistance. For example, for the SOT-89-3 package θ JA=101°C/W,
TJ(MAX)=150°C and using TA=25°C, the maximum power dissipation is 1.23W.
The derating factor (-1/θJA)=-9.9mW/°C. Below 25°C the power dissipation figure can be increased by
9.9mW per degree and similarly decreased by this factor for temperatures above 25°C.
Note 6: Typical values represent the most typical parametric norm.
Note 7: Dropout voltage is measured by reducing VIN until VOUT drops to 98% of its nominal value.
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Dec. 2011
Revision: 0.2
5/12
5 Page 
ESMT/EMP
Preliminary
EMP8046
Revision History
Revision
0.1
0.2
Date
2010.09.12
2011.12.02
Description
Original
Modify the output voltage range.
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Dec. 2011
Revision: 0.2
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet EMP8046-50VB03NRR.PDF ] | |
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