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PDF HDMP-1646A Data sheet ( Hoja de datos )
| Número de pieza | HDMP-1646A | |
| Descripción | Gigabit Ethernet and Fibre Channel SerDes ICs | |
| Fabricantes | Agilent | |
| Logotipo |  |
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Gigabit Ethernet and
Fibre Channel SerDes ICs
Technical Data
Features
• IEEE 802.3z Gigabit Ethernet
Compatible
• ANSI x3.230-1994 Fibre
Channel Compatible (FC-O)
• Supports Serial Data Rates of
1062.5 MBd (Fibre Channel)
& 1250 MBd (Gigabit
Ethernet)
• Low Power Consumption,
630 mW Typical
• Transmitter and Receiver
Functions Incorporated onto
a Single IC
• Three Package Sizes
Available:
– 10 mm TQFP (HDMP-T1636A)
– 10 mm PQFP (HDMP-1636A)
– 14 mm PQFP (HDMP-1646A)
• 10-Bit Wide Parallel TTL
Compatible I/Os
• Single +3.3 V Power Supply
• 5-Volt Tolerant I/Os
• 2 kV ESD Protection on All
Pins
Applications
• 1250 MBd Gigabit Ethernet
Interface
• 1062.5 MBd Fibre Channel
Interface
• Mass Storage System I/O
Channel
• Work Station/Server I/O
Channel
• Backplane Serialization
• FC Interface for Disk Drives
and Arrays
Description
The HDMP-1636A/46A/T1636A
transceiver is a single integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet,
1062.5 MBd Fibre Channel, and
proprietary link interfaces. It
provides complete Serialize/
Deserialize (SerDes) for copper
transmission, incorporating the
Gigabit Ethernet/Fibre Channel
transmit and receive functions
into a single device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with the IEEE 802.3z
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
serializes this data into a high
speed serial data stream. The
parallel data is expected to be
“8B/10B” encoded data, or equiv-
alent. This parallel data is latched
into the input register of the
transmitter section on the rising
edge of the reference clock (used
as the transmit byte clock). A
1062.5 MHz reference clock is
used in Fibre Channel operation,
whereas a 125 MHz reference
clock is used in Gigabit Ethernet
operation.
HDMP-1636A Transceiver
HDMP-1646A Transceiver
HDMP-T1636A Transceiver
The transmitter section’s PLL
locks to the user supplied
reference byte clock. This clock
is then multiplied by 10 to gener-
ate the high speed serial clock
used to generate the high speed
output. The high speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber optic module for optical
transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd or 1250 MBd and
recovers the original 10-bit wide
parallel data. The receiver PLL
locks onto the incoming serial
signal and recovers the high
speed serial clock and data. The
serial data is converted back into
10-bit parallel data, recognizing
the 8B/10B comma character to
establish byte alignment.
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
1 page  
5
HDMP-1636/1646A/T1636A (Transmitter Section) – Fibre Channel
Timing Characteristics
TA[1] = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
Units
Min.
Typ.
tsetup
Setup Time
nsec 2
thold
t_txlat[2]
Hold Time
Transmitter Latency
nsec
nsec
1.5
4.2
bits 4.4
Max.
Notes:
1. Device tested and characterized under TA conditions specified, with TC monitored at approximately 20° higher than TA.
2. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).
REFCLK
TX[0]-TX[9]
DATA
DATA
DATA
tSETUP
tHOLD
Figure 3. Transmitter Section Timing.
DATA
DATA
1.4 V
2.0 V
0.8 V
DATA BYTE A
DATA BYTE B
± DOUT T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5
t_TXLAT
TX[0]-TX[9]
DATA BYTE B
DATA BYTE C
REFCLK
1.4 V
Figure 4. Transmitter Latency.
5 Page 
11
HDMP-1636A/1646A/T1636A (Transmitter Section)
Output Jitter Characteristics
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
RJ[1]
Random Jitter at DOUT, the High Speed Electrical Data Port, specified as
one sigma deviation of the 50% crossing point (RMS)
DJ[1] Deterministic Jitter at DOUT, the High Speed Electrical Data Port (pk-pk)
Units
ps
ps
Typ.
8
15
Note: 1. Defined by Fibre Channel Specification X3.230-1994 FC-PH Standard, Annex A, Section A.4 and tested using measurement
method shown in Figure 8.
70841B
PATTERN
GENERATOR*
0000011111
+ DATA
- DATA
1.25 GHz
125 MHz
83480A
OSCILLOSCOPE
TRIGGER
CH1 CH2
70311A
CLOCK SOURCE
* PATTERN
GENERATOR
PROVIDES A
DIVIDE BY
10 FUNCTION.
BIAS
TEE
+DOUT -DOUT
HDMP-1636A
REFCLK LOOPEN
Tx[0..9]
1.4 V
0011111000
(STATIC K28.7)
70311A
CLOCK SOURCE
DIVIDE
BY 10
CIRCUIT
(DUAL
OUTPUT)
1.25 GHz
DIVIDE
BY 2
CIRCUIT
70841B
PATTERN
GENERATOR
+K28.5, -K28.5
+ DATA
- DATA
83480A
OSCILLOSCOPE
TRIGGER
CH1 CH2
VARIABLE
DELAY
TTL
125 MHz
+DOUT -DOUT
-DIN
+DIN
HDMP-1636A
REFCLK
ENBYTSYNC
LOOPEN
Tx[0..9] Rx[0..9]
a. Block Diagram of RJ Measurement Method.
Figure 8. Transmitter Jitter Measurement Method.
b. Block Diagram of DJ Measurement Method.
HDMP-1636A/1646A/T1636A
Package Thermal Characteristics
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
PDmax
θJA[1]
Power Dissipationa
Thermal Resistance: Junction to Ambient in still air
HDMP-1646A
HDMP-1636A
HDMP-T1636A
ψJT[2]
Thermal Characterization parameter: Junction to package top
HDMP-1646A
HDMP-1636A
HDMP-T1636A
Units
mW
°C/W
°C/W
Typ.
675
Max.
900
36.3
45.0
40.0
9.6
7.8
6.2
Notes:
Based on independent testing done by Agilent.
1. θJA is based on thermal measurement in a still air environment at 23°C on a standard 3 x 3” FR4 PCB as specified in EIA/JESD 51-7.
2. ψJT is used to determine the actual junction temperature in a given application, using the following equation:
TJ = ψJT x PD + TT where TT is the measured temperature on top center of the package and PD is the power being dissipated.
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet HDMP-1646A.PDF ] | |
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