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PDF AD7453 Data sheet ( Hoja de datos )
| Número de pieza | AD7453 | |
| Descripción | 12-Bit ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7453 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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FEATURES
Specified for VDD of 2.7 V to 5.25 V
Low power at max throughput rate:
3.3 mW max at 555 kSPS with VDD = 3 V
7.25 mW max at 555 kSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 µA max
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
GENERAL DESCRIPTION
The AD74531 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
pseudo differential analog input. This part operates from a
single 2.7 V to 5.25 V power supply and features throughput
rates up to 555 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input frequen-
cies up to 3.5 MHz. The reference voltage for the AD7453 is
applied externally to the VREF pin and can range from 100 mV to
VDD, depending on the power supply and what suits the
application.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled on
the falling edge of CS; the conversion is also initiated at this
point.
The SAR architecture of this part ensures that there are no
pipeline delays. The AD7453 uses advanced design techniques
to achieve very low power dissipation.
Pseudo Differential, 555 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7453
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN–
VREF
12-BIT
T/H SUCCESSIVE
APPROXIMATION
ADC
AD7453
CONTROL LOGIC
SCLK
SDATA
CS
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. Operation with 2.7 V to 5.25 V Power Supplies.
2. High Throughput with Low Power Consumption. With a
3 V supply, the AD7453 offers 3.3 mW max power
consumption for a 555 kSPS throughput rate.
3. Pseudo Differential Analog Input.
4. Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also
features a shutdown mode to maximize power efficiency at
lower throughput rates.
5. Variable Voltage Reference Input.
6. No Pipeline Delay.
7. Accurate control of the sampling instant via a CS input and
once-off conversion control.
8. ENOB > 10 bits Typically with 500 mV Reference.
1Protected by U.S. Patent Number 6,681,332.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD7453
Parameter
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2
Throughput Rate
POWER REQUIREMENTS
VDD
IDD7, 8
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down Mode
Test Conditions/Comments
1.6 µs with a 10 MHz SCLK
Sine wave input
Full-scale step input
SCLK on or off
VDD = 4.75 V to 5.25 V
VDD= 2.7 V to 3.6 V
SCLK on or off
VDD = 5 V; 1.55 mW typ for 100 kSPS7
VDD = 3 V; 0.64 mW typ for 100 kSPS7
VDD = 5 V; SCLK on or off
VDD = 3 V; SCLK on or off
A Version1 B Version1 Unit
16 16 SCLK cycles
250 250 ns max
290 290 ns max
555 555 kSPS max
2.7/5.25
2.7/5.25
V min/max
0.5 0.5 mA typ
1.5 1.5 mA max
1.2 1.2 mA max
1 1 µA max
7.25 7.25 mW max
3.3 3.3 mW max
5 5 µW max
3 3 µW max
1 Temperature ranges as follows: A, B versions: –40°C to +85°C.
2 See Terminology section.
3 Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
4 A small dc input is applied to VIN– to provide a pseudo ground for VIN+.
5 The AD7453 is functional with a reference input in the range 100 mV to VDD.
6 Guaranteed by characterization.
7 See Power vs. Throughput Rate section.
8 Measured with a full-scale dc input.
Rev. B | Page 4 of 20
5 Page 
AD7453
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
0
POSITIVE DNL
NEGATIVE DNL
1234
VREF (V)
Figure 11. Change in DNL vs. VREF for VDD = 5 V
5
5
4
3
2
1 POSITIVE INL
0
NEGATIVE INL
–1
–2
01234
VREF (V)
Figure 12. Change in INL vs. VREF for VDD = 5 V
5
12
VDD = 3V
11
10
9
8
7
VDD = 5V
6
01
23
VREF (V)
4
Figure 13. ENOB vs. VREF for VDD = 3 V and 5 V
5
Rev. B | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD7453.PDF ] | |
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