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PDF AD7452 Data sheet ( Hoja de datos )
| Número de pieza | AD7452 | |
| Descripción | 12-Bit ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Specified for VDD of 3 V and 5 V
Low power at max throughput rate:
3.3 mW max at 555 kSPS with 3 V supplies
7.25 mW max at 555 kSPS with 5 V supplies
Fully differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 µA max
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
Motor control
GENERAL DESCRIPTION
The AD74521 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
fully differential analog input. This part operates from a single
3 V or 5 V power supply and features throughput rates up to
555 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies up to 3.5 MHz. The reference voltage is applied
externally to the VREF pin and can be varied from 100 mV to
3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines the
common-mode voltage range of the part. With this truly
differential input structure and variable reference input, the
user can select a variety of input ranges and bias points.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled on
the falling edge of CS, and the conversion is also initiated at this
point.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Differential Input, 555 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7452
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN–
VREF
12-BIT
T/H SUCCESSIVE
APPROXIMATION
ADC
AD7452
CONTROL LOGIC
SCLK
SDATA
CS
GND
Figure 1.
The SAR architecture of this part ensures that there are no
pipeline delays.
The AD7452 uses advanced design techniques to achieve very
low power dissipation.
PRODUCT HIGHLIGHTS
1. Operation with Either 3 V or 5 V Power Supplies.
2. High Throughput with Low Power Consumption. With a
3 V supply, the AD7452 offers 3.3 mW max power
consumption for 555 kSPS throughput.
3. Fully Differential Analog Input.
4. Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also
features a shutdown mode to maximize power efficiency at
lower throughput rates.
5. Variable Voltage Reference Input.
6. No Pipeline Delay.
7. Accurate Control of the Sampling Instant via a CS Input
and Once-Off Conversion Control.
8. ENOB > 8 Bits Typically with 100 mV Reference.
1 Protected by U.S. Patent Number 6,681,332.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD7452
Parameter
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time3
Throughput Rate
POWER REQUIREMENTS
VDD
IDD9, 10
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down
Test Conditions/Comments
1.6 µs with a 10 MHz SCLK
Sine wave input
Step input
Range: 3 V + 20%/–10%;
5 V ± 5%
SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK on or off
VDD = 5 V, 1.55 mW typ for 100 kSPS9
VDD = 3 V, 0.64 mW typ for 100 kSPS9
VDD = 5 V, SCLK on or off
VDD = 3 V, SCLK on or off
B Version2
16
200
290
555
2.7/5.25
0.5
1.5
1.2
1
7.25
3.3
5
3
Unit
SCLK cycles
ns max
ns max
kSPS max
V min/V max
mA typ
mA max
mA max
µA max
mW max
mW max
µW max
µW max
1 Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 23 and Figure 24.
2 Temperature ranges as follows: B Version: –40°C to +85°C.
3 See Terminology section.
4 Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
5 Because the input spans of VIN+ and VIN– are both VREF and are 180° out of phase, the differential voltage is 2 × VREF.
6 The AD7452 is functional with a reference input from 100 mV; for VDD = 5 V, the reference can range up to 3.5 V.
7 The AD7452 is functional with a reference input from 100 mV; for VDD = 3 V, the reference can range up to 2.2 V.
8 Guaranteed by characterization.
9 See Power vs. Throughput Rate section.
10 Measured with a midscale dc input.
Rev. B | Page 4 of 28
5 Page 
AD7452
AD7452–TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, fS = 555 kSPS, fSCLK = 10 MHz, unless otherwise noted.
75 0
VDD = 5.25V
VDD = 4.75V
–20
70
VDD = 3.6V
–40
VDD = 2.7V
–60
65
–80
8192 POINT FFT
fSAMPLE = 555kSPS
fIN = 100kSPS
SINAD = 71.7dB
THD = –82dB
SFDR = –83dB
60
55
10
100
FREQUENCY (kHz)
277
Figure 5. SINAD vs. Analog Input Frequency for Various Supply Voltages
–100
–120
–140
0
100 200
FREQUENCY (kHz)
Figure 8. Dynamic Performance with VDD = 5 V
277
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10
VDD = 3V
VDD = 5V
100 1000
FREQUENCY (kHz)
10000
Figure 6. CMRR vs. Frequency for VDD = 5 V and 3 V
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
CODE
3072
Figure 9. Typical DNL for VDD = 5 V
4096
0
100mV p-p SINE WAVE ON VDD
NO DECOUPLING ON VDD
–20
–40
–60
VDD= 3V
–80 VDD= 5V
–100
–120
0
100 200 300 400 500 600 700 800 900 1000
SUPPLY RIPPLE FREQUENCY (kHz)
Figure 7. PSRR vs. Supply Ripple Frequency without Supply Decoupling
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
CODE
3072
Figure 10. Typical INL for VDD = 5 V
4096
Rev. B | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD7452.PDF ] | |
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