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PDF NCP3101CMNTXG Data sheet ( Hoja de datos )
| Número de pieza | NCP3101CMNTXG | |
| Descripción | Wide Input Voltage Synchronous Buck Converter | |
| Fabricantes | ON Semiconductor | |
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NCP3101C
Wide Input Voltage
Synchronous Buck Converter
The NCP3101C is a high efficiency, 6 A DC−DC buck converter
designed to operate from a 5 V to 12 V supply. The device is capable
of producing an output voltage as low as 0.8 V. The NCP3101C can
continuously output 6 A through MOSFET switches driven by an
internally set 275 kHz oscillator. The 40−pin device provides an
optimal level of integration to reduce size and cost of the power
supply. The NCP3101C also incorporates an externally compensated
transconductance error amplifier and a capacitor programmable
soft−start function. Protection features include programmable short
circuit protection and input under voltage lockout (UVLO). The
NCP3101C is available in a 40−pin QFN package.
Features
• Split Power Rail 2.7 V to 18 V on PWRVCC
• 275 kHz Internal Oscillator
• Greater Than 90% Max Efficiency
• Boost Pin Operates to 35 V
• Voltage Mode PWM Control
• 0.8 V $1% Internal Reference Voltage
• Adjustable Output Voltage
• Capacitor Programmable Soft−Start
• 85% Max Duty Cycle
• Input Undervoltage Lockout
• Resistor Programmable Current Limit
• These are Pb−Free Devices
Applications
• Servers / Networking
• DSP and FPGA Power Supply
• DC−DC Regulator Modules
D1
CBST
CPHS BST
CIN PWRVCC PWRPHS
PWRVCC
EP
VCC
PWRPHS
(EP)
PWRGND
CVCC
BG
COMP/DIS
PWRGND
(EP)
RSET
CP FC
AGND
(EP)
FB
AGND
CC
LO
CO
100
95
90
85
R1 80
75
70
65
R2 60
55
50 0
Figure 1. Typical Application Diagram
http://onsemi.com
MARKING
DIAGRAM
1 40
QFN40, 6x6
CASE 485AK
NCP3101C
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 24 of this data sheet.
VIN = 5 V
VIN = 12 V
VOUT = 3.3 V
123 45 6
IOUT (A)
Figure 2. Efficiency
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 1
1
Publication Order Number:
NCP3101C/D
1 page  
NCP3101C
Table 3. ELECTRICAL CHARACTERISTICS (−40°C < TJ < 125°C; VCC =12 V, BST − PHS = 12 V, BST = 12 V, PHS = 24 V,
for min/max values unless otherwise noted).
Characteristic
Power Power Channel
Input Voltage Range
Boost Voltage Range
SUPPLY CURRENT
Quiescent Supply Current
Quiescent Supply Current
VCC Supply Current
VCC Supply Current
Boost Quiescent Current
Shutdown Supply Current
UNDER VOLTAGE LOCKOUT
VCC UVLO Threshold
VCC UVLO Hysteresis
BST UVLO Threshold Rising
BST UVLO Threshold Falling
SWITCHING REGULATOR
VFB Feedback Voltage,
Control Loop in Regulation
Oscillator Frequency
Ramp−Amplitude Voltage
Minimum Duty Cycle
Maximum Duty Cycle
TG Falling to BG Rising Delay
BG Falling to TG Rising Delay
PWM COMPENSATION
Transconductance
Open Loop DC Gain
Output Source Current
Output Sink Current
Input Bias Current
ENABLE
Enable Threshold (Falling)
SOFT−START
Delay to Soft−Start
SS Source Current
Switch Over Threshold
Conditions
PWRVCC − GND
VCC − GND
VBST − GND
Min
2.7
4.5
4.5
VFB = 0.85 V VCOMP = 0.4 V,
No Switching, VCC = 13.2 V
VFB = 0.85 V VCOMP = 0.4 V
No Switching, VCC = 5.0 V
VFB = VCOMP = 1 V, Switching, VCC = 13.2 V
VFB = VCOMP = 1 V, Switching, VCC = 5 V
VFB = 0.85 V, No Switching, VCC = 13.2 V
VFB = 1 V, VCOMP= 0 V, No Switching, VCC = 13.2 V
−
VCC Rising Edge
−
BST Rising
3.8
−
−
−
Typ
4.1
3.2
9.1
4.8
63
4.1
−
364
3.82
3.71
Max
18
13.2
26.5
15
8.0
−
4.3
−
−
−
Unit
V
V
V
mA
mA
mA
mA
mA
mA
V
mV
V
V
0°C < TJ < 70°C, 4.5 V < VCC < 13.2 V
−40°C < TJ < 125°C, 4.5 < VCC < 13.2 V
0°C <
−40°C
<TJT<J
<701°2C5,°4C.,54V.5<<VVCCCC<<1133.2.2VV
VCC = 12 V, TG < 2.0 V, BG > 2.0 V
VCC = 12 V, BG < 2.0 V, TG > 2.0 V
Guaranteed by design
VFB < 0.8 V
VFB > 0.8 V
0.792
0.788
250
233
0.8
−
0.800
0.800
275
275
1.1
7.0
88.5
46
41
0.808
0.812
300
317
1.4
−
V
kHz
V
%
%
ns
ns
3.1 − 3.5
55 70
−
80 140 200
80 131 200
−
0.160
1.0
mS
DB
mA
mA
0.37 0.4
.43
V
VFB < 0.8 V
VFB = 0.8 V
1 − 5 ms
− 10.6 −
mA
− 100 − % of
Vref
OVER−CURRENT PROTECTION
OCSET Current Source
OC Threshold
OC Switch−Over Threshold
Fixed OC Threshold
PWM OUTPUT STAGE
High−Side Switch On−Resistance
Low−Side Switch On−Resistance
Sourced from BG Pin before Soft−Start
RBG = 5 kW
VCC = 12 V ID = 1 A
VCC = 12 V ID = 1 A
− 10 − mA
− 50 − mV
− 700 − mV
− 99 − mV
− 18 − mW
− 18 − mW
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5
5 Page 
NCP3101C
LS Gate Drive
2V
BG Comparator
2V
HS Gate Drive
Switch Node Comparator
2V
Switch Node
SCP Trip Voltage
C Phase
SCP Comparator/
Latch Output
Figure 24. Switching and Current Limit Timing
Overcurrent Threshold Setting
The NCP3101C overcurrent threshold can be set from
50 mV to 450 mV by adding a resistor (RSET) between BG
and GND. During a short period of time following VCC
rising above the UVLO threshold, an internal 10 mA current
(IOCSET) is sourced from the BG pin, creating a voltage
drop across RSET. The voltage drop is compared against a
stepped internal voltage ramp. Once the internal stepped
voltage reaches the RSET voltage, the value is stored
internally until power is cycled. The overall time length for
the OC setting procedure is approximately 3 ms. When
connecting an RSET resistor between BG and GND, the
programmed threshold will be:
IOCth
+
IOCSET * RSET
RDS(on)
³
7.2
A
+
10
mA
18
* 13
mW
kW
(eq. 1)
IOCSET
= Sourced current
IOCTH
= Current trip threshold
RDS(on)
= On resistance of the low side MOSFET
RSET
= Current set resistor
The RSET values range from 5 kW to 45 kW. If RSET is
not connected or the RSET value is too high, the device
switches the OCP threshold to a fixed 96 mV value (5.3 A)
typical at 12 V. The internal safety clamp on BG is triggered
as soon as BG voltage reaches 700 mV, enabling the 96 mV
fixed threshold and ending the OC setting period. The
current trip threshold tolerance is $25 mV. The accuracy is
best at the highest set point (550 mV). The accuracy will
decrease as the set point decreases.
Drivers
The NCP3101C drives the internal high and low side
switching MOSFETS with 1 A gate drivers. The gate drivers
also include adaptive non−overlap circuitry. The
non−overlap circuitry increases efficiency which minimizes
power dissipation by minimizing the low−side MOSFET
body diode conduction time.
A block diagram of the non−overlap and gate drive
circuitry used is shown in Figure 24.
UVLO
FAULT
BST
TG
+
- 2V
PHASE
PWM
OUT
+
- 2V
UVLO
FAULT
Figure 25. Block Diagram
VCC
BG
GND
Careful selection and layout of external components is
required to realize the full benefit of the onboard drivers.
The capacitors between VCC and GND and between BST
and CPHS must be placed as close as possible to the IC. A
ground plane should be placed on the closest layer for return
currents to GND in order to reduce loop area and inductance
in the gate drive circuit.
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| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet NCP3101CMNTXG.PDF ] | |
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