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PDF HY512264TC Data sheet ( Hoja de datos )
| Número de pieza | HY512264TC | |
| Descripción | Extended Data Out mode 4M bit dynamic RAM | |
| Fabricantes | Hyundai Electronics | |
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HY512264
128Kx16, Extended Data Out mode
DESCRIPTION
This family is a 4M bit dynamic RAM organized 131,072 x 16-bit configuration with CMOS DRAMs. The circuit and process
design allow this device to achieve high performance and low power dissipation. In dependant read and write of upper and
lower byte is controlled by 2 separate /CAS inputs. Optional features are access time(50, 60 or 70ns), package type(SOJ,
TSOP-II), and power onsumption (Normal or Low power with self refresh). Hyundai’s advanced circuit design and process
technology allow this device to achieve high bandwidth, low power consumption and high reliability.
FEATURES
Ÿ Extended data out operation
Ÿ Read-modify-write Capability
Ÿ 2/CAS inputs for upper and lower byte control
Ÿ TTL compatible inputs and outputs
Ÿ /CAS-before-/RAS, /RAS-only, Hidden and
Self refresh capability
Ÿ Max. Active power dissipation
Speed
50
60
70
Power
605mW
550mW
495mW
Ÿ Refresh cycle
Part number
HY512264
Refresh
512
Normal
8ms
SL-part
128ms
Ÿ JEDEC standard pinout
Ÿ 40-pin Plastic SOJ (400mil)
40/44-pin plastic TSOP-II (400mil)
Ÿ Single power supply of 5V ± 10%
Ÿ Early Write or output enable controlled write
Ÿ Fast access time and cycle time
Speed
50
60
70
tRAC
50ns
60ns
70ns
tCAC
15ns
17ns
20ns
tHPC
20ns
24ns
29ns
ORDERING INFORMATION
Part Name
HY512264JC
HY512264LJC
HY512264SLJC
HY512264TC
HY512264LTC
HY512264SLTC
*SL : Low power with self refresh
Refresh
512
512
512
512
512
512
Power
L-part
SL-part
L-part
SL-part
Package
40Pin SOJ
40Pin SOJ
40Pin SOJ
40/44Pin TSOP-II
40/44Pin TSOP-II
40/44Pin TSOP-II
This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of
circuits described. No patent licences are implied
Rev.10 / Jan.97
1
Hyundai Semiconductor
1 page  
HY512264
DC CHARACTERISTICS
(TA = 0°C to 70°C , VCC = 5V ± 10%, VSS = 0V, unless otherwise noted.)
Symbol
Parameter
Test condition
ICC1 Operating Current
/RAS, /CAS Cycling
tRC = tRC(min.)
ICC2 TTL Standby
Current
/RAS, /CAS ≥ VIH(min)
Other inputs ≥ VSS
ICC3 /RAS-only Refresh
Current
/RAS Cycling,/CAS = VIH
tRC = tRC(min.)
ICC4
EDO mode Current
/CAS Cycling, /RAS = VIL
tHPC = tHPC(min.)
ICC5 CMOS Standby
Current
/RAS = /CAS ≥ VCC - 0.2V
ICC6 /CAS-before-/RAS
Refresh Current
/RAS & /CAS = 0.2V
tRC = tRC(min.)
ICC7 Battery Back-up
Current (SL-part)
tRC=125µs
/CAS = CBR cycling or 0.2V
/OE & /WE = VCC - 0.2V
Address = Vcc-0.2V or 0.2V
DQ0~DQ15 = Vcc-0.2, 0.2V or Open
ICC8
Self Refresh Current
/RAS & /CAS = 0.2V
(SL-part)
Other pins are same as ICC7
Speed
50
60
70
50
60
70
50
60
70
L-part
50
60
70
tRAS ≤
1µs
Max.
110
100
90
2
110
100
90
100
100
90
1
200
100
110
100
400
Unit
mA
mA
mA
mA
mA
µA
mA
µA
400 µA
Note
1. ICC1, ICC3, ICC4, ICC6 and ICC7 depend on output loading and cycle rates(tRC and tHPC).
2. Specified values are obtained with output unloaded.
3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4,
address can be changed maximum once while /CAS=VIH withen one Extened Data Out mode cycle time tPC.
4. Only tRAS(max) = 1µs is applied to refresh of battery backup but tRAS(max) = 10µs is to applied to normal functional
operation.
5. Icc5(max.), Icc7 and Icc8 are applied to SL-part only.
6. Operating condition for 50ns part is Vcc=5V¡ ¾5%,Cout 30pF.
128Kx16,EDO DRAM
Rev.10 / Jan.97
5
5 Page | ||
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| PDF Descargar | [ Datasheet HY512264TC.PDF ] | |
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