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PDF HD74LVC74 Data sheet ( Hoja de datos )
| Número de pieza | HD74LVC74 | |
| Descripción | Dual D-type Flip Flops with Preset and Clear | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74LVC74
Dual D-type Flip Flops with Preset and Clear
ADE-205-066C(Z)
Rev.3
September 1995
Description
The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin
package. The logic level present at the data input is transferred to the output during the positive going
transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level
at the appropriate input. Low voltage and high speed operation is suitable at the battery drive product (note
type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
• VCC = 2.0 V to 5.5 V
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V to 5.5 V)
1 page  
HD74LVC74
Switching Characteristics
Item
Symbol
Maximum clock frequency fmax
VCC (V)
2.7
3.3±0.3
5.0±0.5
Propagation delay time
t PLH
t PHL
2.7
3.3±0.3
5.0±0.5
tPLH 2.7
tPHL 3.3±0.3
5.0±0.5
Setup time
tsu 2.7
3.3±0.3
5.0±0.5
Hold time
th 2.7
3.3±0.3
5.0±0.5
Pulse width
tw 2.7
3.3±0.3
5.0±0.5
2.7
3.3±0.3
5.0±0.5
Recovery time
trec 2.7
3.3±0.3
5.0±0.5
Input capacitance
CIN 2.7
Output capacitance CO 2.7
Ta = –40 to 85°C
Min Typ Max
150.0 — —
150.0 — —
150.0 — —
— 6.0 9.0
1.5 5.0 8.0
— 4.0 6.5
— 6.5 9.0
1.5 5.0 8.0
— 4.0 6.5
4.0 — —
3.0 — —
3.0 — —
2.0 — —
2.0 — —
2.0 — —
4.0 — —
4.0 — —
4.0 — —
6.0 — —
5.0 — —
4.0 — —
3.0 — —
2.0 — —
2.0 — —
— 3.0 —
— 15.0 —
Unit From (Input)
MHz
MHz
MHz
ns CLK
ns
ns
ns PR or CLR
ns
ns
ns
ns
ns
ns
ns
ns
ns CK
ns
ns
ns PR or CLR
ns
ns
ns
ns
ns
pF
pF
To (Output)
Q, Q
Q, Q
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HD74LVC74.PDF ] | |
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