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PDF HD74LVC573A Data sheet ( Hoja de datos )
| Número de pieza | HD74LVC573A | |
| Descripción | Octal D-type Transparent Latches with 3-state Outputs | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74LVC573A
Octal D-type Transparent Latches with 3-state Outputs
ADE-205-116B(Z)
3rd Edition
December 1996
Description
The HD74LVC573A has eight D type latches with three state outputs in a 20 pin package. When the latch
enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D
inputs will be retained at the outputs until latch enable returns high again. When a high logic level is
applied to the output control input, all outputs go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage elements. Low voltage and high speed operation is
suitable at the battery drive product (note type personal computer) and low power consumption extends the
life of a battery for long time operation.
Features
• VCC = 2.0 V to 5.5 V
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V to 5.5 V)
Function Table
Inputs
OC LE
D
Output Q
L HHH
L HL L
L L X Q0
HXXZ
H : High level
L : Low level
X : Immaterial
Z : High impedance
Q0 : Level of Q before the indicated steady input conditions were established.
1 page  
HD74LVC573A
Switching Characteristics
Ta = –40 to 85°C
Item
Propagation delay time
Symbol VCC (V)
tPLH 2.7
tPHL 3.3±0.3
5.0±0.5
Min Typ Max
— — 9.0
1.5 — 8.0
— — 6.5
tPLH 2.7
— — 9.5
tPHL 3.3±0.3 1.5 — 8.5
5.0±0.5 — — 7.0
Output enable time
t ZH
t ZL
2.7
3.3±0.3
5.0±0.5
——
1.5 —
——
9.5
8.5
7.0
Output disable time
t HZ
t LZ
2.7
3.3±0.3
5.0±0.5
——
1.5 —
——
8.5
7.5
6.5
Setup time
tsu 2.7
2.0 — —
3.3±0.3 2.0 — —
5.0±0.5 2.0 — —
Hold time
th 2.7
1.5 — —
3.3±0.3 1.5 — —
5.0±0.5 1.5 — —
Pulse width
tw 2.7
3.3 — —
3.3±0.3 3.3 — —
5.0±0.5 3.3 — —
Between output
pins skew *1
t OSLH
2.7
———
t OSHL
3.3±0.3 — — 1.0
5.0±0.5 — — 1.0
Input capacitance
CIN 2.7
— 3.0
Output capacitance
CO
2.7
— 15.0
Note: 1. This parameter is characterized but not tested.
tosLH = | tPLHm - tPLHn|, tosHL = | tPHLm - tPHLn|
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
From (Input) To (Output)
DQ
LE Q
OC Q
OC Q
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HD74LVC573A.PDF ] | |
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