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PDF HD74LVC16373A Data sheet ( Hoja de datos )
| Número de pieza | HD74LVC16373A | |
| Descripción | 16-bit D-type Transparent Latches with 3-state Outputs | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74LVC16373A
16-bit D-type Transparent Latches with 3-state Outputs
ADE-205-121B(Z)
3rd Edition
December 1996
Description
The HD74LVC16373A has sixteen D type latches with three state outputs in a 48 pin package. When the
latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at
the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is
applied to the output control input (1G, 2G), all outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the storage elements. Low voltage and high speed
operation is suitable at the battery drive product (note type personal computer) and low power consumption
extends the life of a battery for long time operation.
Features
• VCC = 2.0 V to 5.5 V
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V to 5.5 V)
Function Table
Inputs
G LE D Output Q
HX XZ
LHLL
L H HH
L L X Q0
H: High level
L: Low level
X: Immaterial
Z: High impedance
Q0: Level of Q before the indicated steady input conditions were established.
1 page  
HD74LVC16373A
Switching Characteristics
Ta = –40 to 85°C
Item
Propagation delay time
Symbol
t PLH
t PHL
VCC (V)
2.7
3.3±0.3
5.0±0.5
Min
—
1.5
—
Typ Max Unit
— 7.7 ns
— 7.0 ns
— 5.5 ns
tPLH 2.7 — — 8.0 ns
tPHL 3.3±0.3 2.0 — 7.0 ns
5.0±0.5 — — 5.5 ns
Output enable time
tZH 2.7 — — 8.0 ns
tZL 3.3±0.3 1.5 — 7.0 ns
5.0±0.5 — — 6.0 ns
Output disable time
tHZ 2.7 — — 8.0 ns
tLZ 3.3±0.3 1.5 — 7.0 ns
5.0±0.5 — — 6.0 ns
Setup time
tsu 2.7 2.0 — — ns
3.3±0.3 2.0 — — ns
5.0±0.5 2.0 — — ns
Hold time
th 2.7 1.5 — — ns
3.3±0.3 1.5 — — ns
5.0±0.5 1.5 — — ns
Pulse width
tw 2.7 3.0 — — ns
3.3±0.3 3.0 — — ns
5.0±0.5 3.0 — — ns
Between output pins skew *1 tOSLH
t OSHL
2.7 — — — ns
3.3±0.3 — — 1.0 ns
5.0±0.5 — — 1.0 ns
Input capacitance
CIN 2.7 — 3.0
Output capacitance
CO 2.7 — 15.0
Note: 1. This parameter is characterized but not tested.
tosLH = | tPLHm – tPLHn |, tosHL = | tPHLm – tPHLn |
—
—
pF
pF
From (Input) To (Output)
DQ
LE Q
GQ
GQ
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HD74LVC16373A.PDF ] | |
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