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PDF ADuM3154 Data sheet ( Hoja de datos )
| Número de pieza | ADuM3154 | |
| Descripción | 7-Channel Digital Isolator | |
| Fabricantes | Analog Devices | |
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Data Sheet
3.75 kV, 7-Channel, SPIsolator
Multiple Slave, Digital Isolator for SPI
ADuM3154
FEATURES
Supports up to 17 MHz SPI clock speed
4 high speed, low propagation delay, SPI signal isolation
channels
Supports up to 4 slave devices
20-lead SSOP package with 5.1 mm creepage
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/µs
Safety and regulatory approvals
UL recognition per UL 1577
3750 V rms for 1 minute
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 565 V peak
APPLICATIONS
Industrial programmable logic controllers (PLCs)
Sensor isolation
GENERAL DESCRIPTION
The ADuM31541 is an SPIsolator™ digital isolator optimized for
a serial peripheral interface (SPI) that includes support for up to
four slave devices. Based on the Analog Devices, Inc., iCoupler®
chip scale transformer technology, the low propagation delay and
jitter in the CLK, MO/SI, MI/SO, and SS SPI bus signals support
SPI clock rates of up to 17 MHz.
The ADuM3154 isolator also provides a slave select multiplexing
system that allows up to four slave devices to be serviced from
one isolator. When a target slave is selected, the slave select
signal propagates to the desired output with low propagation
delay, allowing tight timing control. The isolated SSx is addressed
through a 250 kbps low speed, 2-channel address bus, allowing
the target slave device to be changed in as little as 2.5 µs.
FUNCTIONAL BLOCK DIAGRAM
VDD1 1
GND1 2
MCLK 3
MO 4
MI 5
MSS 6
ADuM3154
ENCODE
ENCODE
DECODE
ENCODE
SSA0 7
SSA1 8
NIC 9
CONTROL
BLOCK
GND1 10
DECODE
DECODE
ENCODE
DECODE
MUX
CONTROL
BLOCK
NIC = NOT INTERNALLY CONNECTED
Figure 1.
20 VDD2
19 GND2
18 SCLK
17 SI
16 SO
15 SS0
14 SS1
13 SS2
12 SS3
11 GND2
Table 1. Related Products
Product
Description
ADuM3150
3. 75 kV, high speed, clock
delayed SPIsolator
ADuM3151/ADuM3152/ 3.75 kV, multichannel SPIsolator
ADuM3153
ADuM4150
5 kV, high speed, clock delayed
SPIsolator
ADuM4151/ADuM4152/ 5 kV, multichannel SPI solator
ADuM4153
ADuM4154
5 kV, multiple slave SPIsolator
1 Protected by U.S. Patents 5,952,849; 6,262,600; 6,873,065; and 7075329. Other patents are pending.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADuM3154
Data Sheet
Table 3. For All Models1, 2, 3
Parameter
SUPPLY CURRENT
A Grade and B Grade
B Grade
DC SPECIFICATIONS
MCLK, MSS, MO, SO, SSA0, SSA1
Input Threshold
Logic High
Logic Low
Input Hysteresis
Input Current per Channel
SCLK, MI, SI, SS0, SS1, SS2, SS3
Output Voltages
Logic High
Logic Low
VDD1, VDD2 Undervoltage Lockout
Supply Current for High Speed Channels
Dynamic Input
Dynamic Output
Supply Current for All Low Speed Channels
Quiescent Input
Quiescent Output
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity4
Symbol Min
IDD1
IDD2
IDD1
IDD2
Typ Max
4.8 8.5
6.5 13
10 18
13.5 19
Unit
mA
mA
mA
mA
Test Conditions/Comments
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
VIH
VIL
VIHYST
II
0.7 × VDDx
−1
500
+0.01
0.3 × VDDx
+1
V
V
mV
µA
0 V ≤ VINPUT ≤ VDDx
VOH
VOL
UVLO
IDDI(D)
IDDO(D)
IDD1(Q)
IDD2(Q)
tR/tF
|CM|
VDDx − 0.1
VDDx − 0.4
5.0
4.8
0.0
0.2
0.1
0.4
2.6
0.080
0.046
4.2
6.1
2.5
25 35
V IOUTPUT = −20 µA, VINPUT = VIH
V IOUTPUT = −4 mA, VINPUT = VIH
V IOUTPUT = 20 µA, VINPUT = VIL
V IOUTPUT = 4 mA, VINPUT = VIL
V
mA/Mbps
mA/Mbps
mA
mA
ns
kV/µs
10% to 90%
VINPUT = VDDx, VCM = 1000 V,
transient magnitude = 800 V
1 VDDx = VDD1 or VDD2.
2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, SSA0, or SSA1 pins.
3 IOUTPUT is the output current of any of the SCLK, MI, SI, SS0, SS1, SS2, or SS3 pins.
4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 4 of 22
5 Page 
ADuM3154
Data Sheet
Table 9. For All Models1, 2, 3
Parameter
SUPPLY CURRENT
A Grade and B Grade
B Grade
DC SPECIFICATIONS
MCLK, MSS, MO, SO, SSA0, SSA1
Input Threshold
Logic High
Logic Low
Input Hysteresis
Input Current per Channel
SCLK, MI, SI, SS0, SS1, SS2, SS3
Output Voltages
Logic High
Logic Low
VDD1, VDD2 Undervoltage Lockout
Supply Current for All Low Speed Channels
Quiescent Input
Quiescent Output
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity4
Symbol Min
IDD
IDD2
IDD
IDD2
Typ Max
3.4 6.5
6.5 13
11.7 15
13.5 19
Unit
mA
mA
mA
mA
VIH
VIL
VIHYST
II
0.7 × VDDx
−1
500
+0.01
0.3 × VDDx
+1
V
V
mV
µA
VOH
VOL
UVLO
IDD1Q)
IDD2(Q)
tR/tF
|CM|
VDDx − 0.1
VDDx − 0.4
5.0
4.8
0.0
0.2
2.6
2.9
6.1
2.5
25 35
0.1
0.4
V
V
V
V
V
mA
mA
ns
kV/µs
Test Conditions/Comments
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
0 V ≤ VINPUT ≤ VDDx
IOUTPUT = −20 µA, VINPUT = VIH
IOUTPUT = −4 mA, VINPUT = VIH
IOUTPUT = 20 µA, VINPUT = VIL
IOUTPUT = 4 mA, VINPUT = VIL
10% to 90%
VINPUT = VDDx, VCM = 1000 V,
transient magnitude = 800 V
1 VDDx = VDD1 or VDD2.
2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, SSA0, or SSA1 pins.
3 IOUTPUT is the output current of any of the SCLK, MI, SI, SS0, SS1, SS2, or SS3 pins.
4 |CM| is the maximum common-mode voltage slew rate that can be sustained whereas maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
PACKAGE CHARACTERISTICS
Table 10.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
IC Junction to Case Thermal Resistance
Symbol Min Typ
RI-O 1012
CI-O 1.0
CI 4.0
θJC 68.5
Max Unit Test Conditions/Comments
Ω
pF f = 1 MHz
pF
°C/W 4-layer JEDEC test board, JESD 51-7 specification
1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
Rev. A | Page 10 of 22
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ADuM3154.PDF ] | |
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