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PDF ADuM3153 Data sheet ( Hoja de datos )
| Número de pieza | ADuM3153 | |
| Descripción | SPIsolator Digital Isolators | |
| Fabricantes | Analog Devices | |
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Data Sheet
3.75 kV, 7-Channel,
SPIsolator Digital Isolators for SPI
ADuM3151/ADuM3152/ADuM3153
FEATURES
Supports up to 17 MHz SPI clock speed
4 high speed, low propagation delay, SPI signal isolation
channels
Three 250 kbps data channels
20-lead SSOP package with 5.1 mm creepage
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognition per UL 1577
3750 V rms for 1 minute
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 565 V peak
APPLICATIONS
Industrial programmable logic controllers (PLCs)
Sensor isolation
GENERAL DESCRIPTION
The ADuM3151/ADuM3152/ADuM31531 are 7-channel,
SPIsolator™ digital isolators optimized for isolated serial peripheral
interfaces (SPIs). Based on the Analog Devices, Inc., iCoupler®
chip scale transformer technology, the low propagation delay in
the CLK, MO/SI, MI/SO, and SS SPI bus signals supports SPI
clock rates of up to 17 MHz. These channels operate with 14 ns
propagation delay and 1 ns jitter to optimize timing for SPI.
The ADuM3151/ADuM3152/ADuM3153 isolators also provide
three additional independent low data rate isolation channels in
three different channel direction combinations. Data in the slow
channels is sampled and serialized for a 250 kbps data rate with
up to 2.5 μs of jitter in the low speed channels.
FUNCTIONAL BLOCK DIAGRAMS
VDD1 1
GND1 2
MCLK 3
MO 4
MI 5
MSS 6
ADuM3151
ENCODE
ENCODE
DECODE
ENCODE
VIA 7
VIB 8
VOC 9
CONTROL
BLOCK
GND1 10
DECODE
DECODE
ENCODE
DECODE
CONTROL
BLOCK
20 VDD2
19 GND2
18 SCLK
17 SI
16 SO
15 SSS
14 VOA
13 VOB
12 VIC
11 GND2
Figure 1. ADuM3151 Functional Block Diagram
VDD1 1
GND1 2
MCLK 3
MO 4
MI 5
MSS 6
ADuM3152
ENCODE
ENCODE
DECODE
ENCODE
VIA 7
VOB 8
VOC 9
CONTROL
BLOCK
GND1 10
DECODE
DECODE
ENCODE
DECODE
CONTROL
BLOCK
20 VDD2
19 GND2
18 SCLK
17 SI
16 SO
15 SSS
14 VOA
13 VIB
12 VIC
11 GND2
Figure 2. ADuM3152 Functional Block Diagram
VDD1 1
GND1 2
MCLK 3
MO 4
MI 5
MSS 6
VOA 7
VOB 8
VOC 9
GND1 10
ADuM3153
ENCODE
ENCODE
DECODE
ENCODE
CONTROL
BLOCK
DECODE
DECODE
ENCODE
DECODE
CONTROL
BLOCK
20 VDD2
19 GND2
18 SCLK
17 SI
16 SO
15 SSS
14 VIA
13 VIB
12 VIC
11 GND2
Figure 3. ADuM3153 Functional Block Diagram
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADuM3151/ADuM3152/ADuM3153
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL =15 pF and CMOS signal levels, unless otherwise noted.
Table 4. Switching Specifications
Parameter
MCLK, MO, SO
SPI Clock Rate
Data Rate Fast (MO, SO)
Propagation Delay
Pulse Width
Pulse Width Distortion
Codirectional Channel
Matching1
Jitter, High Speed
MSS
Data Rate Fast
Propagation Delay
Pulse Width
Pulse Width Distortion
Setup Time2
Jitter, Low Speed
VIA, VIB, VIC
Data Rate Slow
Propagation Delay
Pulse Width
Jitter, Low Speed
VIx3 Minimum Input Skew4
Symbol
SPIMCLK
DRFAST
tPHL, tPLH
PW
PWD
tPSKCD
JHS
DRFAST
tPHL, tPLH
PW
PWD
MSSSETUP
JLS
DRSLOW
tPHL, tPLH
PW
JLS
tVIx SKEW3
A Grade
Min Typ Max
100
1
1
2
30
3
4
100
1.5
2.5
2
30
3
250
0.1 2.6
4
2.5
10
B Grade
Min Typ Max
12.5
1
12.5
34
20
3
2
12.5
10
2.5
34
30
3
250
0.1 2.6
4
2.5
10
Unit
MHz
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ns
ns
ns
kbps
µs
µs
µs
ns
Test Conditions/Comments
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
Within PWD limit
50% input to 50% output
Within PWD limit
|tPLH − tPHL|
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3 VIx = VIA, VIB, or VIC.
4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Table 5. Supply Current
Device Number
ADuM3151
ADuM3152
ADuM3153
Symbol
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
1 MHz, A Grade/B Grade
Min Typ Max
2.8 6.5
4.6 8
3.4 6
5.0 8
2.8 5.5
3.5 9
17 MHz, B Grade
Min Typ Max Unit Test Conditions/Comments
10.5 18
mA CL = 0 pF, low speed channels
9.0 17
mA CL = 0 pF, low speed channels
11.7 18
10.0 16
mA CL = 0 pF, low speed channels
mA CL = 0 pF, low speed channels
11.7 18
10.0 15
mA CL = 0 pF, low speed channels
mA CL = 0 pF, low speed channels
Rev. A | Page 5 of 22
5 Page 
Data Sheet
ADuM3151/ADuM3152/ADuM3153
REGULATORY INFORMATION
The ADuM3151/ADuM3152/ADuM3153 are approved by the organizations listed in Table 14. See Table 19 and the Insulation Lifetime
section for the recommended maximum working voltages for specific cross isolation waveforms and insulation levels.
Table 14.
UL
Recognized under 1577 Component
Recognition Program1
3750 V rms Single Protection
File E214100
CSA
Approved under CSA Component Acceptance
Notice #5A
Basic insulation per CSA 60950-1-07+A1+A2
and IEC 60950-1 2nd Ed.+A1+A2, 510 V rms
(721 V peak) maximum working voltage3
File 205078
VDE
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Reinforced insulation, 565 V peak
File 2471900-4880-0001
1 In accordance with UL 1577, each model is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (current leakage detection limit = 10 μA).
2 In accordance with DIN V VDE V 0884-10, each model is proof tested by applying an insulation test voltage ≥ 525 V peak for 1 second (partial discharge detection limit = 5 pC).
The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.
3 See Table 19 for recommended maximum working voltages under various operating conditions.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 15.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol Value
3750
L(I01) 5.1
Minimum External Tracking (Creepage)
L(I02) 5.1
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
CTI
0.017
>400
II
Unit
V rms
mm min
mm min
mm min
V
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303, Part 1
Material group (DIN VDE 0110, 1/89, Table 1)
Rev. A | Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet ADuM3153.PDF ] | |
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