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PDF HD74HC78 Data sheet ( Hoja de datos )
| Número de pieza | HD74HC78 | |
| Descripción | Dual J-K Flip-Flops (with Preset/ Common Clear and Common Clock) | |
| Fabricantes | Hitachi Semiconductor | |
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HD74HC78
Dual J-K Flip-Flops (with Preset, Common Clear and
Common Clock)
Description
This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock
pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are
controlled by a common clear and a common clock. Preset and clear are independent of the clock and
accomplished by a low logic level on the corresponding input.
Features
• High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
1 page  
HD74HC78
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Ta = –40 to
+85°C
Item
Maximum clock
frequency
Symbol
f max
VCC (V)
2.0
4.5
Min Typ Max Min
——6 —
— — 30 —
Max Unit Test Conditions
5 MHz
24
6.0 — — 35 — 28
Propagation delay tPLH
time
t PHL
2.0 — — 150 — 190 ns Clock to Q or Q
4.5 — 20 30 — 38
6.0 — — 26 — 33
2.0 — — 140 — 175
Clear to Q or Q
4.5 — 18 28 — 35
6.0 — — 24 — 30
2.0 — — 140 — 175
Preset to Q or Q
4.5 — 18 28 — 35
6.0 — — 24 — 30
Pulse width tw 2.0 80 — — 100 — ns Clock, Preset, Clear
4.5 16 8 — 20 —
6.0 14 — — 17 —
Setup time
tsu 2.0 100 — — 125 — ns J or K to Clock
4.5 20 2 — 25 —
6.0 17 — — 21 —
Hold time
th 2.0 5 — — 5 — ns Clock to J or K
4.5 5 –1 — 5 —
6.0 5 — — 5 —
Removal time
t rem
2.0 100 — — 125 — ns Preset or Clear to Clock
4.5 20 0 — 25 —
6.0 17 — — 21 —
Output rise/fall
time
t TLH
t THL
2.0 — — 75 — 95 ns
4.5 — 5 15 — 19
6.0 — — 13 — 16
Input capacitance Cin — — 5 10 — 10 pF
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HD74HC78.PDF ] | |
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