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PDF HD74HC73 Data sheet ( Hoja de datos )
| Número de pieza | HD74HC73 | |
| Descripción | Dual J-K Flip-Flops (with Clear) | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74HC74
Dual D-type Flip-Flops (with Preset and Clear)
Description
The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level
present at thte data input is transferred to the output during the positive going transition to the clock pulse.
Preset and clear are independent of the clock and accomplished by a low level at the appropriate input.
Features
• High Speed Operation: tpd (Clock to Q or Q) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
Function Table
Inputs
Preset
Clear
Clock
Data
Outputs
Q
Q
LH X X H L
HL
LL
XX
XX
LH
H*1 H*1
HH
HHL
HH
LLH
HH
L
X
no change
no change
HH
HX
no change
no change
H
Note:
H
X
no change
no change
1. Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable,
if Preset and Clear go HIGH simultaneously.
1 page  
19.20
20.32 Max
14
8
1 1.30 7
2.39 Max
Unit: mm
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25
+
–
0.10
0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
DP-14
Conforms
Conforms
0.97 g
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HD74HC73.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HD74HC73 | Dual J-K Flip-Flops (with Clear) | Hitachi Semiconductor |
| HD74HC74 | Dual D-type Flip-Flops (with Preset and Clear) | Hitachi Semiconductor |
| HD74HC74 | Dual D-type Flip-Flops |  Renesas |
| HD74HC74AP | Dual D-type Flip-Flops (with Preset and Clear) | Hitachi Semiconductor |
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