PDF ADAU1461 Data sheet ( Hoja de datos )

Número de pieza	ADAU1461
Descripción	24-Bit Audio Codec
Fabricantes	Analog Devices
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SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL ADAU1461 FEATURES GENERAL DESCRIPTION SigmaDSP 28-/56-bit, 50 MIPS digital audio processor Fully programmable with SigmaStudio graphical tool 24-bit stereo audio ADC and DAC: >98 dB SNR Sampling rates from 8 kHz to 96 kHz Low power: 17 mW record, 18 mW playback, 48 kHz 6 analog input pins, configurable for single-ended or differential inputs Flexible analog input/output mixers Stereo digital microphone input Analog outputs: 2 differential stereo, 2 single-ended stereo, 1 mono headphone output driver PLL supporting input clocks from 8 MHz to 27 MHz Analog automatic level control (ALC) Microphone bias reference voltage Analog and digital I/O: 3.3 V I2C and SPI control interfaces Digital audio serial data I/O: stereo and time-division multiplexing (TDM) modes Software-controllable clickless mute GPIO pins for digital controls and outputs 32-lead, 5 mm × 5 mm LFCSP −40°C to +105°C operating temperature range Qualified for automotive applications APPLICATIONS Automotive head units Automotive amplifiers Navigation systems Rear-seat entertainment systems The ADAU1461 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback at 35 mW from a 3.3 V analog supply. The stereo audio ADCs and DACs support sample rates from 8 kHz to 96 kHz as well as a digital volume control. The SigmaDSP® core features 28-bit processing (56-bit double precision). The processor allows system designers to compensate for the real-world limitations of microphones, speakers, amplifiers, and listening environments, resulting in a dramatic improvement in the perceived audio quality through equalization, multiband compression, limiting, and third-party branded algorithms. The SigmaStudio™ graphical development tool is used to program the ADAU1461. This software includes audio processing blocks such as filters, dynamics processors, mixers, and low level DSP functions for fast development of custom signal flows. The record path includes an integrated microphone bias circuit and six inputs. The inputs can be mixed and muxed before the ADC, or they can be configured to bypass the ADC. The ADAU1461 includes a stereo digital microphone input. The ADAU1461 includes five high power output drivers (two differential and three single-ended), supporting stereo head- phones, an earpiece, or other output transducer. AC-coupled or capless configurations are supported. Individual fine level controls are supported on all analog outputs. The output mixer stage allows for flexible routing of audio. FUNCTIONAL BLOCK DIAGRAM JACKDET/MICIN HP JACK REGULATOR DETECTION ADAU1461 LAUX LINP LINN RINP RINN RAUX INPUT MIXERS ALC ADC ADC ADC DAC DIGITAL DIGITAL FILTERS FILTERS DAC DAC OUTPUT MIXERS LOUTP LOUTN LHP MONOOUT RHP ROUTP ROUTN MICBIAS MICROPHONE BIAS PLL SERIAL DATA INPUT/OUTPUT PORTS I2C/SPI CONTROL PORT MCLK ADDR0/ ADDR1/ SCL/ SDA/ CLATCH CDATA CCLK COUT Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. 1 page Parameter Total Harmonic Distortion + Noise Line Output Mode Headphone Output Mode Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Mute Attenuation Mixer 3 and Mixer 4 Muted Mixer 5, Mixer 6, and Mixer 7 Muted All Volume Controls Muted Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio DAC TO HEADPHONE/EARPIECE OUTPUT Full-Scale Output Voltage (0 dB) Total Harmonic Distortion + Noise Capless Headphone Mode Headphone Output Mode Interchannel Isolation Power Supply Rejection Ratio REFERENCE Common-Mode Reference Output Test Conditions/Comments 0 dBFS, 10 kΩ load Line output mode MX3RM, MX3LM, MX4RM, MX4LM = 0, MX3AUXG[3:0], MX4AUXG[3:0] = 0000, MX3G1[3:0], MX3G2[3:0] = 0000, MX4G1[3:0], MX4G2[3:0] = 0000 MX5G3[1:0], MX5G4[1:0], MX6G3[1:0], MX6G4[1:0], MX7[1:0] = 00 LOUTM, ROUTM = 0 MONOM, LHPM, RHPM = 0 1 kHz, 0 dBFS input signal CM capacitor = 20 μF, 100 mV p-p @ 1 kHz LOUTx, ROUTx, LHP, RHP in headphone output mode; PO = output power per channel Scales linearly with AVDD −4 dBFS, 16 Ω load, PO = 21.1 mW −4 dBFS, 32 Ω load, PO = 10.6 mW −2 dBFS, 16 Ω load −2 dBFS, 32 Ω load 0 dBFS, 10 kΩ load 1 kHz, 0 dBFS input signal, 32 Ω load Referred to GND Referred to CM (capless headphone mode) CM capacitor = 20 μF, 100 mV p-p @ 1 kHz CM pin Min −0.3 −22 −10 1.62 ANALOG PERFORMANCE SPECIFICATIONS, −40°C < TA < +105°C IOVDD = 3.3 V ± 10%. Table 2. Parameter SINGLE-ENDED LINE INPUT Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Input Mixer Gain per Step Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Test Conditions/Comments 20 Hz to 20 kHz, −60 dB input −1 dBFS −12 dB to +6 dB range LINPG[2:0], LINNG[2:0] = 000, RINPG[2:0], RINNG[2:0] = 000, MX1AUXG[2:0], MX2AUXG[2:0] = 000 Min 74 71 2.88 −0.5 −5 −22 Rev. 0 \| Page 5 of 88 ADAU1461 Typ Max Unit −92 −77 dB −89 −79 dB 101 dB 98 dB −85 −78 dB −89 −82 −74 −0.005 0 +3 100 70 −80 −74 −69 +0.3 +22 +10 dB dB dB dB mV % dB dB 0.92 (2.60) −82 −82 −78 −75 −86 −71 −65 −77 73 50 67 1.65 1.67 V rms (V p-p) dB dB dB dB dB dB dB dB V Typ Max Unit dB dB −67 dB 3.09 dB −77 dB +0.5 dB +5 mV −6 % 5 Page CLATCH CCLK CDATA COUT tCLS tCDS tCCPH tCCPL tCDH Figure 4. SPI Port Timing ADAU1461 tCLH tCLPH tCOD SDA SCL tSCH tSCR tDS tSCLH tSCH tSCLL tSCF tSCS Figure 5. I2C Port Timing CLK DATA1/ DATA2 DATA1 tDCF tDCR tDDH DATA2 tDDH tDDV DATA1 tDDV DATA2 tBFT Figure 6. Digital Microphone Timing Rev. 0 \| Page 11 of 88 11 Page

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