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PDF ADAU1401A Data sheet ( Hoja de datos )
| Número de pieza | ADAU1401A | |
| Descripción | SigmaDSP 28-/56-Bit Audio Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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SigmaDSP 28-/56-Bit Audio Processor
with Two ADCs and Four DACs
ADAU1401A
FEATURES
GENERAL DESCRIPTION
28-/56-bit, 50 MIPS digital audio processor
2 ADCs: SNR of 100 dB, THD + N of −83 dB
4 DACs: SNR of 104 dB, THD + N of −90 dB
Complete standalone operation
Self-boot from serial EEPROM
Auxiliary ADC with 4-input mux for analog control
GPIOs for digital controls and outputs
Fully programmable with SigmaStudio graphical tool
28-bit × 28-bit multiplier with 56-bit accumulator for full
double-precision processing
Clock oscillator for generating master clock from crystal
PLL for generating master clock from 64 × fS, 256 × fS,
384 × fS, or 512 × fS clocks
Flexible serial data input/output ports with I2S-compatible,
left-justified, right-justified, and TDM modes
Sampling rates of up to 192 kHz supported
On-chip voltage regulator for compatibility with 3.3 V systems
48-lead, plastic LQFP
APPLICATIONS
Multimedia speaker systems
MP3 player speaker docks
Automotive head units
Minicomponent stereos
Digital televisions
Studio monitors
Speaker crossovers
Musical instrument effects processors
In-seat sound systems (aircraft/motor coaches)
The ADAU1401A is a complete, single-chip audio system with
28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like
control interfaces. Signal processing includes equalization, cross-
over, bass enhancement, multiband dynamics processing, delay
compensation, speaker compensation, and stereo image widening.
This processing can be used to compensate for real-world limita-
tions of speakers, amplifiers, and listening environments, providing
dramatic improvements in perceived audio quality.
The signal processing of the ADAU1401A is comparable to that
found in high end studio equipment. Most processing is done in
full 56-bit, double-precision mode, resulting in very good low
level signal performance. The ADAU1401A is a fully program-
mable DSP. The easy to use SigmaStudio™ software allows the
user to graphically configure a custom signal processing flow
using blocks such as biquad filters, dynamics processors, level
controls, and GPIO interface controls.
The ADAU1401A programs can be loaded on power-up either
from a serial EEPROM through its own self-boot mechanism or
from an external microcontroller. On power-down, the current
state of the parameters can be written back to the EEPROM from
the ADAU1401A to be recalled the next time the program is run.
Two Σ-Δ ADCs and four Σ-Δ DACs provide a 98.5 dB analog
input to analog output dynamic. Each ADC has a THD + N of
−83 dB, and each DAC has a THD + N of −90 dB. Digital input
and output ports allow a glueless connection to additional ADCs
and DACs. The ADAU1401A communicates through an I2C® bus
or a 4-wire SPI port.
FUNCTIONAL BLOCK DIAGRAM
DIGITAL VDD DIGITAL GROUND
3.3V
3
3
ANALOG VDD ANALOG PLL MODE PLL LOOP
GROUND
FILTER
3 23
CRYSTAL
2
2-CHANNEL
ANALOG
INPUT
1.8V
REGULATOR
FILTA/
ADC_RES 2
STEREO
ADC
ADAU1401A
PLL CLOCK OSCILLATOR
28-/56-BIT, 50MIPS
AUDIO PROCESSOR CORE, 40ms DELAY MEMORY
DAC
DAC
2 FILTD/CM
4-CHANNEL
ANALOG
OUTPUT
RESET/
MODE
SELECT
CONTROL INTERFACE
AND SELF-BOOT
8-CHANNEL 8-BIT AUX
DIGITAL INPUT
ADC
GPIO
8-CHANNEL
DIGITAL OUTPUT
INPUT/OUTPUT MATRIX
RESET SELF-BOOT
5
I2C/SPI AND WRITEBACK
3
DIGITAL IN OR GPIO
Figure 1.
3
AUX ADC OR GPIO
3
DIGITAL OUT OR GPIO
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
ADAU1401A
POWER
Table 4.
Parameter
SUPPLY VOLTAGE
Analog Voltage
Digital Voltage
PLL Voltage
IOVDD Voltage
SUPPLY CURRENT
Analog Current (AVDD and PVDD)
Digital Current (DVDD)
Analog Current, Reset
Digital Current, Reset
DISSIPATION
Operation (AVDD, DVDD, PVDD)2
Reset, All Supplies
POWER SUPPLY REJECTION RATIO (PSRR)
1 kHz, 200 mV p-p Signal at AVDD
Min
Typ
3.3
1.8
3.3
3.3
50
25
35
1.5
259.5
118
50
Max1
85
40
55
4.5
Unit
V
V
V
V
mA
mA
mA
mA
mW
mW
dB
1 Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
2 Power dissipation does not include IOVDD power because the current drawn from this supply is dependent on the loads at the digital output pins.
TEMPERATURE RANGE
Table 5.
Parameter
Functionality Guaranteed
Min Typ Max Unit
−40
+105
°C ambient
PLL AND OSCILLATOR
Table 6.
Parameter1
PLL Operating Range
PLL Lock Time
Crystal Oscillator Transconductance (gm)
Min
MCLK_Nom − 20%
Typ
78
Max
MCLK_Nom + 20%
20
Unit
MHz
ms
mmho
1 Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
REGULATOR
Table 7.
Parameter1
DVDD Voltage
Min Typ
1.7 1.8
1 Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit.
Max
1.84
Unit
V
Rev. 0 | Page 5 of 5
5 Page 
ADAU1401A
Pin No.
14
15
16
17
18
19
20
21
22
23
26
27
28
29
30
31
32
33
34
35
36, 48
Mnemonic
MP7/SDATA_OUT1
MP6/SDATA_OUT0/
TDM_IN
MP10/OUTPUT_LRCLK
VDRIVE
IOVDD
MP11
ADDR1/CDATA/WB
CLATCH/WP
SDA/COUT
SCL/CCLK
MP9/SDATA_OUT3/
AUX_ADC0
MP8/SDATA_OUT2/
AUX_ADC3
MP3/SDATA_IN3/
AUX_ADC2
MP2/SDATA_IN2/
AUX_ADC1
RSVD
OSCO
MCLKI
PGND
PVDD
PLL_LF
AVDD
Type 1
D_IO
D_IO
D_IO
A_OUT
PWR
D_IO
D_IN
D_IO
D_IO
D_IO
D_IO/A_IO
D_IO/A_IO
D_IO/A_IO
D_IO/A_IO
D_OUT
D_IN
PWR
PWR
A_OUT
PWR
Description
Multipurpose GPIO/Serial Output Port Data 1. See the Multipurpose Pins section for
more details.
Multipurpose GPIO/Serial Output Port Data 0/TDM Data Input. See the Multipurpose Pins
section for more details.
Multipurpose GPIO/Serial Output Port LRCLK. See the Multipurpose Pins section for
more details.
Drive for 1.8 V Regulator. The base of the voltage regulator external PNP transistor is
driven from VDRIVE. See the Voltage Regulator section for details.
Supply for Input and Output Pins. The voltage on this pin sets the highest input voltage that
should be seen on the digital input pins. This pin is also the supply for the digital output signals
on the control port and MPx pins. IOVDD should always be set to 3.3 V. The current draw of this
pin is variable because it is dependent on the loads of the digital outputs.
Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK). See the Multipurpose Pins
section for more details.
I2C Address 1/SPI Data Input/EEPROM Writeback Trigger. ADDR1 in combination with ADDR0
sets the I2C address of the IC so that four ADAU1401A devices can be used on the same I2C
bus (see the I2C Port section for details). For more information about the CDATA function of this
pin, see the SPI Port section. A rising (default) or falling (if set by EEPROM messages) edge
on the WB pin triggers a writeback of the interface registers to the external EEPROM. This
function can be used to save parameter data on power-down (see the Self-Boot section
for details).
SPI Latch Signal/Self-Boot EEPROM Write Protect. CLATCH must go low at the beginning of an
SPI transaction and high at the end of a transaction. Each SPI transaction can take a different
number of cycles on the CCLK pin to complete, depending on the address and read/write
bit that are sent at the beginning of the SPI transaction (see the SPI Port section for details). The
WP pin is an open-collector output when the device is in self-boot mode. The ADAU1401A
pulls WP low to enable writes to an external EEPROM. This pin should be pulled high to
3.3 V (see the Self-Boot section for details).
I2C Data/SPI Data Output. SDA is a bidirectional open collector. The line connected to SDA
should have a 2.2 kΩ pull-up resistor (see the I2C Port section for details). COUT is used for
reading back registers and memory locations. It is three-stated when an SPI read is not
active (see the SPI Port section for details).
I2C Clock/SPI Clock. SCL is always an open-collector input when in I2C control mode. In
self-boot mode, SCL is an open-collector output (I2C master). The line connected to SCL
should have a 2.2 kΩ pull-up resistor (see the I2C Port section for details). CCLK can either
run continuously or be gated off between SPI transactions (see the SPI Port section for details).
Multipurpose GPIO/Serial Output Port Data 3/Auxiliary ADC Input 0. See the Multipurpose
Pins section for more details.
Multipurpose GPIO/Serial Output Port Data 2/Auxiliary ADC Input 3. See the Multipurpose
Pins section for more details.
Multipurpose GPIO/Serial Input Port Data 3/Auxiliary ADC Input 2. See the Multipurpose
Pins section for more details.
Multipurpose GPIO/Serial Input Port Data 2/Auxiliary ADC Input 1. See the Multipurpose
Pins section for more details.
Reserved. Tie this pin to ground, either directly or through a pull-down resistor.
Crystal Oscillator Circuit Output. A 100 Ω damping resistor should be connected between
this pin and the crystal. This output should not be used to directly drive a clock to another
IC. If the crystal oscillator is not used, this pin can be left unconnected. See the Using the
Oscillator section for details.
Master Clock Input. This pin can either be connected to a 3.3 V clock signal or be the input
from the crystal oscillator circuit. See the Setting Master Clock/PLL Mode section for details.
PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. PGND should be decoupled to PVDD with a 100 nF capacitor.
3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. This pin should be
decoupled to PGND with a 100 nF capacitor.
PLL Loop Filter Connection. Two capacitors and a resistor must be connected to this pin, as
shown in Figure 15. See the Setting Master Clock/PLL Mode section for more details.
3.3 V Analog Supply. This pin should be decoupled to AGND with a 100 nF capacitor.
Rev. 0 | Page 11 of 11
11 Page | ||
| Páginas | Total 52 Páginas | |
| PDF Descargar | [ Datasheet ADAU1401A.PDF ] | |
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